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Power up: Summit to highlight power-wise design tips

Posted: 13 Aug 2007 ?? ?Print Version ?Bookmark and Share

Keywords:Power up summit? power-wise designs? low-power systems?

Power consumption is one of the many things engineers have to keep track when doing their designs. Power use has a cascading effect from the component level such as transceivers, processors and regulators to the application level, including smart phones, mobile TV and portable media players. A keen awareness of power consumption is critical in the design stage.

On August 23, Cadence Design Systems Inc., IntellaSys Corp., Mentor Graphics, ON Semiconductor and MontaVista Software Inc. will expound on the topic: Powering Down. This summit is one of the highlights of the 7th Embedded Systems Conference-Taiwan (ESC-Taiwan) and the 15th EDA & Test-Taiwan Conference & Exhibition (EDA&T-Taiwan), which will take place simultaneously at the Taipei International Convention Center and will run until August 24.

Issues to discuss
Design teams are increasingly adopting low power techniques such as multisupply voltage (MSV) and power shut-off (PSO) to meet power requirements while keeping in mind stringent functionality and performance targets. However, the techniques usually employed affect the entire design flow methodology and can compromise productivity. Wei-Lii Tan of Cadence will shed more light into this problem and discuss a potential solution in the summit Building low power intent into then design flow.

Meanwhile, the immense popularity of consumer electronics is driving chipmakers to deliver more performance-per-watt. IntellaSys' Joseph Wang's discussion, Scaling embedded arrays to conserve power, will highlight an approach that integrates an array of processor cores with analog functions and a flexible I/O on a single chip. By eliminating the central clock and activating each core only when it is needed, substantial power savings result.

Is your low-power design switched on? This is the question Stewart Li of Mentor Graphics will be asking during the summit. In developing various systems from mobile handsets to portable navigation systems to computer severs, engineers need to consider the management of system power to boost battery life and the reduction of power use and heat generation. While several design techniques have been employed, low-power design is still a challenge for system developers.

The efficiency targets on the other hand for desktop and server power supplies are fueled further by the US 80 PLUS initiative and the new Energy Star requirements. Alvin Chang of ON Semiconductor will touch on the requirements, outline the approach for the ATX reference design and present the salient results that slash power losses by about 50 percent in the summit ATX design exceeds new efficiency standards.

The goal of a dynamic power management (DPM) is to enable fine-grained control of system process and devices for the maximum allowable power usage for any given operating state. In addition, DPM allows the development of a power management scheme tailored to a particular system. In the summit Using dynamic power management to minimize consumption, Julian Hsu of MontaVista Software will talk about the Mobilinux 5.0, which has the ability to control device power state on per application and per device basis.

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