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Managing embedded memory at 45nm

Posted: 16 Aug 2007 ?? ?Print Version ?Bookmark and Share

Keywords:manage embedded memory? 45nm node memory? memory technology challenges?

Within a short time, embedded designers will face major challenges associated with embedded memory at or around the 45nm technology node. Industry leaders have already declared that conventional SRAM, flash and DRAM will encounter scalability and endurance issues at those feature sizes.

Consequently, embedded memory management not only takes on new meaning but also faces different design perspectives and associated challenges. That's because memory chip makers are altering once-stable architectures and technologies to comply with scalability and endurance demands. To fend off those inevitabilities, conventional memory vendors are attempting to shoehorn more circuitry into already well-altered and crowded architectures, while newcomers try different technology routes.

Meanwhile, microprocessor makers are pushing for increasingly higher performance. These newer, more powerful microprocessors with embedded memory management units (MMUs) will pose their own set of design issues as they confront conventional memory problems at or around 45nm. Those basic issues may be exacerbated by newer memory technologies such as first-generation magnetoresistive RAM (MRAM) and phase-change RAM (PRAM).

MMUs are expected to metamorphose into more complex structures to meet the demands of highly advanced SoCs populated with multiple embedded processors. For example, recent research has led to dynamic two-level memory management, said to be faster than software-based memory management.

More challenges
With conventional memory nearing its normal life cycle because of its inability to keep up with smaller feature sizes, memory management faces even more difficulties than the usual ones. It becomes the recipient of a new onslaught of still-to-be-defined problem areas brought about by changes in conventional memory and unproven technologies. Those unknowns are chiefly concerned with questions relating to how additional memory circuits, revised architectures and new material technologies will play with emerging MMU hardware and software techniques.

The best way to maintain efficient MMU operations for embedded designs is to keep memory simple and straightforward. An ideal architecture is one that delivers proven scalability and unlimited endurance, as well as fast switching, low power and high speed. To date, few memory developers have tapped into the rich source providing these key embedded design benefits. That source is spintronics, or spin electronics, which refers to devices that rely on an electron's spin to perform their functions. The spin is an electron quantum property and is associated with magnetism.

Managing spin
Historically, chipmakers and electronic systems OEMs have relied on charge-based devices. Conventional electronic components move electric charges around in a silicon chip or IP core. The spin associated with each electron has generally not been used, though.

Grandis engineers recently invented ways to manipulate the electron's spin to create universal non-volatile memory circuitry called spin-transfer torque (STT)-RAM. Nanomagnets are used to control the spin. By passing electrons through the nanomagnet, the spin of electrons goes in the same magnetization direction as the nanomagnet.

A magnetic tunnel junction (MTJ) is at the center of an STT-RAM bit cell. It is composed of two ferromagnetic electrodes with a thin insulating layer in between. The storage or free layer is the top nanomagnet. The middle is the barrier. The "pinned" layer or spin filter is the bottom nanomagnet.

Current flows in a perpendicular fashion directly through each STT-RAM bit to address each one individually. Writing errors are thus eliminated.

Spin transfer switching shifts the MTJ's state from antiparallel or 1 to parallel or 0 and vice versa. This is performed by perpendicularly running current from the top to the bottom of the MTJ, and vice versa. STT-RAM addresses each bit individually by flowing current directly through the bit. Consequently, unintended writing errors are eliminated.

Spin-polarized currents perform switching. By polarizing the current via the STT method, data is passed from the fixed MTJ layer or polarizer to the free MTJ layer. Current running through the fixed layer polarizes the electrons. The polarized electrons then affect the switching of the free layerhence, the parallel and antiparallel configurations.

A bit line, cladding and write word line create a magnetic field in a conventional MRAM to switch '0' and '1' states.

STT-RAM is ideal for future MRAM produced using ultrafine processes. It not only presents fewer if any MMU issues, but it also can be efficiently embedded in new generations of FPGAs, microprocessors, MCUs and SoC devices. And because STT-RAM requires internal voltage of only 1.2V, it can operate with a single 1.5V battery.

On the other hand, DRAM and flash require charge pumps to supply higher voltages. Existing NAND flash technology requires the internal voltage to be raised to 10-12V for write operations. That voltage is boosted with the help of a charge pump, which requires considerable power and presents adverse design conditions for embedded designers.

Another major benefit of STT-RAM is low writing current on the order of 100-200?A at the 90nm node. At the 45nm node and beyond, writing current continues to scale down significantly below 100?A. This lower current translates into denser, less expensive memory.

Factors such as scalability, endurance and current switching can have a direct impact on the demands of increasingly higher memory management efficiencies.

- Farhad Tabrizi
President and CEO, Grandis Inc.

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