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Implement the right flash memory interface

Posted: 16 Aug 2007 ?? ?Print Version ?Bookmark and Share

Keywords:flash memory interface? NAND flash memory? reduce BOM flash?

Consumer-class, mobile product designers are constantly looking for high-capacity storage to enable their products to save more pictures, movies, MP3s or simple data files. NAND flash memory meets these demands with single-level cell (SLC) and multilevel cell (MLC) technologies.

For designs using midrange densities, SLC NAND flash is a good alternative. Current SLC NAND devices require only single-bit error correction code (ECC) per 512bytes. As SLC NAND geometries shrink, it's anticipated that ECC requirements for these devices will only increase slightly. Next-generation wireless and embedded processors will include more sophisticated ECC capabilities, providing direct support for future SLC NAND flash memory.

Current MLC devices require 4bits of ECC for each 512byte sector. With future generations of MLC NAND flash, ECC requirements are expected to exceed 8bit correction for each 512byte sector. Such advanced ECC circuits are implemented in the NAND flash controller hardware within the processor. Thus, care must be taken to ensure that the processor supports the ECC requirements of the NAND flash device.

Added to this consideration is the need for an efficient interface between the processor and the flash memory. Designers can perform smooth implementation by selecting an interface supported by many processors.

Rapidly changing requirements present obvious design challenges for embedded system designers and processor vendors. In addition to hardware ECC requirements, there are planned architectural changes to improve performance in MLC NAND, such as increasing the page size from 2Kbytes to 4Kbytes and options for dual-plane arrays, which will mandate other changes as well. To keep pace with NAND flash manufacturers, system designers and processor vendors will need to allocate additional resources for hardware and software development, which could be a significant challenge in itself.

Increase compatibility
To minimize the impact of competing and sometimes incompatible NAND flash architectures, several NAND flash suppliers, controller makers and designers have joined together to announce the Open NAND Flash Interface (ONFI) standard. The standard's primary goal is to increase compatibility. It doesn't diminish the importance of embedded processor vendors staying abreast of NAND developments.

Processors providing direct NAND support will typically yield the lowest BOM. However, abstracting the complexities of NAND flash operations insulates designers from concerns relative to technology changes as high-density NAND flash evolves. Additional benefits include potentially shorter development cycles and reduced resource allocations.

In concept, the evolution of NAND flash is similar to the evolution of PC HDDs when they were introduced and the ATA specification was established. Providing a high-level, abstracted interface enables the processor and software to treat NAND flash like simple, block-oriented file systems. It also enables NAND flash management tasks, such as error correction, bad block management and wear leveling, to be incorporated.

Traditional solutions
While several NAND suppliers have tried to solve various aspects of the embedded processor challenge, few have used an abstracted implementation with a standard interface. One configuration, with a processor that supports a direct NAND interface, provides a low-cost solution and relies exclusively on the processor for ECC support. Block management and wear leveling are typically handled in software.

The figure shows the comparison of three available NAND flash configurations. The implementation on the left shows a processor that supports a direct NAND flash interface. The Samsung OneNAND approach is in the center. The right side shows Micron's Managed NAND.

SLC NAND flash requires at least 1bit ECC. While these relatively simple ECC algorithms can be implemented in software, higher-performance applications will require hardware assistance. MLC NAND flash currently requires a minimum of 4bit ECC. Future devices will require more complex ECC and block management, and will continue to escalate the demands on processor-supporting hardware.

Samsung Electronics Co. Ltd has taken an interesting approach with its OneNAND offering, targeting processors that include a NOR-like interface rather than a direct NAND interface. This approach is attractive for low-density designs, but becomes cost-prohibitive when dice are stacked to achieve higher densities. Because each die has roughly 5 percent allocated for the interface, providing multiple dice in one package comes with a significant premium. Samsung has also chosen to integrate 1bit ECC hardware on the die. This addresses the ECC challenge, but leaves block management and driver software to the processor.

Using Micron's Managed NAND, a controller is packaged in a BGA with one or more NAND devices. With the flash managed by the controller, the necessary software support can be provided by a simple, low-level driver. Managing several flash devices with one controller is also a cost-effective approach for any density. The first product offered will be a 1Gbyte part.

Abstracted solutions
Some NAND flash vendors already offer abstracted implementations. The iNAND from SanDisk Corp. includes a secure digital (SD) interface. Managed NAND from Micron uses MMC interface. Most wireless processors include SD or MMC interfaces.

In addition to eliminating NAND dependencies such as SLC/MLC or varying page sizes, these new technologies offload block-management and wear-leveling tasks from the OS to the controller. Depending on the flash support provided by the software, this can potentially save valuable execution time and code-storage space.

With a standard, high-performance MMC interface, Managed NAND supports up to 52MBps (peak) using an 8bit data bus. In addition, the single-controller die can be packaged with various flash components. The common interface, BGA pinout and package design provide a consistent implementation over a range of densities. A less obvious benefit is the ongoing support plan for various densities. Because the interface to the processor doesn't change, the underlying flash technology inside the BGA can change and evolve without impacting the application. This approach extends the longevity of higher-density solutions and makes it possible to support multiple densities with one PCB.

Optimized controller
Managed NAND includes a standard block-level interface, and an error-management and wear-leveling controller, freeing the processor from these tasks. This functionality alone could eliminate the need for a higher-performance processor or additional hardware/software design resources. The controller is optimized to take advantage of specific NAND performance features, including program and read caching. This can provide a performance improvement over other implementations. It's also possible to boot directly from Managed NAND.

For designs requiring low- or medium-density NAND flash, SLC memory will continue to be a good choice. For higher-densities, several processors already support the necessary ECC for today's MLC and future SLC devices. The challenge for next-generation embedded processor designs is to meet the increasing ECC support requirements of future MLC NAND devices.

- Jim Cooke
NAND/MCP Flash Applications Engineering Manager
Micron Semiconductor Products Inc.

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