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Deal with power consumption at chip, system levels

Posted: 16 Aug 2007 ?? ?Print Version ?Bookmark and Share

Keywords:low power technology? chip system level power? power consumption portable devices?

With the great demand for smaller, cheaper, feature-rich portable devices with longer battery lives, portable designers need to aggressively address all aspects of power consumption at both the chip and system levels.

Today, designers are faced with a daunting challenge: insatiable global consumer demand for smaller, cheaper, feature-rich portable devices with longer battery lives. The sheer number of iterations on the same offering will exponentially grow.

System designers are being forced to keep up with the rapidly changing A/V processing standards, and the increasing use of compression and encryption for security. Further, because of the short product life cycles and extreme competition in this marketplace, designers want more features and complexity, but not at the expense of draining the battery. The increasing pressure on energy conservation, the costs of running parallel design teams, creating more complex chips and increasingly expensive mask sets are reducing the ROI of portable systems. Moreover, they are creating the need for innovation and technologies to support these demands.

Companies are talking about reducing energy usage. But to make an impact, we need to aggressively address all aspects of power consumption at both the chip and system levels. By doing so, the industry is answering the call for low-power technology and more important, influencing decisions made about the technologies used in next-generation portable and battery-operated applications.

At the chip level, we've begun to identify design techniques that will aid the delivery of low-power solutions that reduce dynamic and static power consumption with minimal performance impact. These include clock gating, multiple voltage thresholds, dynamic power switching, multiple voltage domains and static leakage power management.

In the FPGA space, for example, new 5?W low-power devices deliver 4x lower static power and as much as 5x longer battery life in portable applications, thus setting a new bar for low-power consumption. Battery-operated portable applications could benefit the most from these user-friendly, low-power implementation options that provide ease-of-use, I/O and clock management, rapid recovery to operation mode and ultra low-power consumption. New families also offer small form factors, support for 1.2V, Advanced Encryption Standard-based secure ISP, immunity to firm errors, live at power-up and low total system cost.

At the board and system levels, power reduction and management are clearly more complex. Multiple power supplies, multiple power rails and varying voltages complicate power management. As a result, the emphasis should be on the development of power-smart systems that only consume power when required, and recognize problems and respective solutions. System partitioning and the selective power up of portions of the system on a need-basis can all be used at the system level, reducing power consumption and offering portable applications longer battery lives.

A live-at-power-up mixed-signal FPGA can offer many benefits to this type of power management control. These FPGAs integrate large blocks of embedded flash memory, programmable logic and configurable analog in a single monolithic device. By integrating large blocks of flash memory, the programmable system chips enable designers to implement a wide range of tasks beyond simple power management. These configurable solutions can monitor single high-voltage sources without external support circuitry and adapt to a board's unique and changing needs, as each unique board design has its own set of power management requirements.

- Dennis Kish
Senior VP of Sales and Marketing, Actel Corp.

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