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DAC5686/DAC5687 clock generation using PLL and external clock modes

Posted: 10 Aug 2007 ?? ?Print Version ?Bookmark and Share

Keywords:DAC? PLL? VCO? external clock modes?

The DAC5686 and DAC5687 both have an onboard PLL and VCO, which allows for some diversity in the input clock, data rates and the update rate of the DAC. There are three stages of interpolation (2x, 4x, and 8x) in the DAC5687 and an extra stage of interpolation (16x) in the DAC5686.

The combination of this with options for interleaved data and a frequency divider in the PLL loop requires some clarification so that the clock modes can be better understood and used properly. The following documentation outlines various modes and settings to help the user understand how the clock modes are being set and the relationships between the input clock, data rate, and the DAC update rate.

There are slight differences between the PLL circuits of the DAC5686 and the DAC5687. The main difference is that the DAC5687 does not have the 16x interpolation and instead has two 4x interpolation modes (X4 and X4L) that use different interpolation filters.

Please view the PDF document for more information.

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