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Synopsys left out in SystemVerilog OVM initiative

Posted: 23 Aug 2007 ?? ?Print Version ?Bookmark and Share

Keywords:SystemVerilog? OVM initiative? Synopsys left out?

Leading EDA firm Synopsys Inc. was not invited to join the Open Verification Methodology (OVM) initiative recently announced by Cadence Design Systems Inc. and Mentor Graphics Corp.

Cadence and Mentor announced they had joined forces to promote a common approach to the verification of design files based on the SystemVerilog language on Aug. 16. They dubbed it the "Open Verification Methodology" or OVM to emphasize that it is an open-source and freely available approach. Executives from the companies claimed that two-thirds of the verification market would support the approach.

However, no attempt was made to persuade the missing thirdSynopsysto join and extend the benefits of OVM industrywide. This was despite the role Synopsys played in the creation of SystemVerilog.

SystemVerilog was created by the donation of the Superlog language to standards-setting body Accellera in 2002 around the time Synopsys acquired Co-Design Automation Inc., the developer of Superlog. Synopsys donated VeraLite, a subset of OpenVera testbench constructs, to Accellera for standardization in SystemVerilog 3.1 to enable engineers to write tests at a higher level of abstraction than offered by Verilog.

Responding to a question as to whether Mentor or Cadence had invited Synopsys to join the OVM initiative, Dennis Brophy, director of strategic business development at Mentor, said: "We did not." Brophy added that communications between the big three companies were reasonably transparent at a high level and said it had seemed that, "the specification of SystemVerilog was as far as they [Synopsys] wanted to go."

Brophy continued: "However, the commitment we make is to the whole industry, including Synopsys. We fulfill the needs of the entire industry."

- Peter Clarke
EE Times Europe




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