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Tilera starts shipping 64-way multiprocessor

Posted: 23 Aug 2007 ?? ?Print Version ?Bookmark and Share

Keywords:Tile64 processor? embedded networking? digital multimedia processing?

Tilera Corp. said it has started shipping its Tile64 processor, a 64-processor chip based on an architecture that could scale to hundreds and even thousands of cores.

The company claimed in a statement that the processor, which is able to run multiple instances of the Linux OS, delivers 10X the performance and 30X the performance-per-watt of the Intel dual-core Xeon and 40X the performance of the leading DSP from Texas Instruments Inc. Initial markets for the Tile64 include embedded networking and digital multimedia processing, Tilera said.

64-processor chip
The Tile64 contains its processors in an 8 by 8 grid with each one capable of between 600 and 900MHz clock frequency while consuming between 170 and 300mW per core. Idle tiles can be put into low-power sleep mode, the company said.

The chip is implemented in a 90nm CMOS manufacturing process and processors handle 32bit data and smaller word sizes, according to a Tilera spokesperson. Overall, the chip can provide up to 192 billion 32bit operations per second or 3BOPS per processor, Tilera stated.

Tilera was founded in 2004 to bring to market the research of Anant Agarwal, who has researched mesh-based multicore architectures since 1996. Agarwal, professor of engineering and computer science at the Massachusetts Institute of Technology, serves as chief technology officer of Tilera and Devesh Garg, a partner at venture capital company Bessemer, serves as CEO. Tilera was admitted to the Silicon 60, EE Times' list of 60 emerging startup companies, in version 6.0 published in June 2007.

Tilera said it holds 40-plus patents pending and claimed to have signed up a dozen customers who are deploying the Tile64 processor in networking and digital multimedia products.

Tile architecture
The scalability of the Tile architecture depends on the iMesh interconnect system which appears to be a conventional Manhattan-style grid architecture, although Tilera claimed it includes a number of patented innovations that enhance the performance and flexibility of the mesh. One such is the ability to create grids as large or as small as an application requires as a means to tailor power consumption. Each of the 64 cores on the Tile64 processor is capable of running its own operating system, such as Linux, and includes L1 and L2 caches, as well as an innovative distributed L3 cache. The cores are overlaid with the iMesh network, providing for silicon area efficiency. The processor integrates four DDR2 memory controllers and a complete array of high speed I/O interfaces, including two 10Gbps XAUI, two 10Gbps PCIe, two 1GbE RGMII and a programmable flexible I/O interface to support interfaces such as compact flash and disk drives.

The Tilera Multicore Development Environment (MDE) is based on Eclipse and and an ANSI standard C compiler, a full-system simulation model. The MDE also provides innovative, graphically driven tools for debugging and profiling multicore processors, and an application level library.

The Tile64 processor is available now in three different device variants based on frequency and I/O capabilities. Production pricing for the Tile64 family starts at $435 in 10,000 unit quantities. Tilera's roadmap also includes plans for a 36-core and a 120-core device.

- Peter Clarke
EE Times Europe




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