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Low-cost FPGAs offer high-speed Serdes

Posted: 03 Sep 2007 ?? ?Print Version ?Bookmark and Share

Keywords:embedded Serdes I/O? low-cost FPGAs? logic macrofunctions? lookup tables?

Lattice Semiconductor Corp. has announced lower price points for the industry's first low-cost FPGAs to offer high-speed embedded Serdes I/O.

Production volume prices have been reduced to as low as $9.95 for the 20k-lookup-table (LUT) LatticeECP2M-20substantially below those of competitive Serdes-capable FPGAs and cracking the $10 price barrier for the first time.

Lattice has also announced that the LatticeECP2M family's performance has been boosted by up to 30 percent across a range of common logic macrofunctions such as decoders, multiplexers, counters and adders. The performance enhancements are supported by Lattice's new-generation ispLever ver 7.0 FPGA design tool suite and are the result of final device characterization along with optimized logic implementation by the design tools.

Lattice is able to offer more-aggressive prices and performance enhancements for the LatticeECP2M FPGAs as the first two family members (with 20k and 35k LUTs) are moved into production. The three remaining family members (50k, 70k and 100k LUTs) will soon be released to volume production.

Lattice and its 90nm foundry partner, Fujitsu Microelectronics America Inc., have worked together to optimize product yields on the LatticeECP2M product family, manufactured on Fujitsu's 300mm wafer fabrication line. Yield expectations for the initial devices have been surpassed at both wafer-level and finished-goods testing.

The latest performance enhancements are a result of the completion of performance characterization of the first devices, as well as the more-efficient logic map, placement and routing functions demonstrated by the ispLever design tools. The enhancements further improve the devices' best-in-class performance in the low-cost FPGA space.

Many basic logic functions have been demonstrated to perform at faster rates than originally specified. For example, 32bit decoders are 30 percent faster, 64bit adders are 22 percent faster and 16bit counters are 7 percent faster. The faster timing specifications and algorithms are incorporated into ispLever ver 7.0.

Representative prices for production volumes (100k pieces or more) purchased directly from Lattice by its customers for delivery in 2008 start at $9.95 for the 20k-LUT device in a 256-ball fine-pitch BGA (fpBGA) package and $46.95 for the 70k-LUT Lattice-ECP2M-70E-5FN900C in a 900-ball fpBGA package.

- Clive Maxfield
Programmable Logic DesignLine

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