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Checking signals on high-density FPGA boards

Posted: 03 Sep 2007 ?? ?Print Version ?Bookmark and Share

Keywords:signal connectivity? FPGA-based board? point-to-point connections? I/O configurations?

Platform verification boards typically have multiple FPGAs and hundreds of signals that are either terminated or non-terminated running between them. Checking the connectivity and locating fabrication and assembly faults becomes a must before the actual bitstream is loaded on the FPGAs for verification.

Such highly dense boards are more prone to assembly faults due to the use of small package resistors and smaller-footprint resistor networks for signal terminations. The following are some reasons why an anomaly could be introduced between the connecting wires on the board:

??Short between the adjacent signals on the terminations provided (resistor networks) or at the FPGA balls;

??Trace cut in the signal due to PCB manufacturing defect or mishandling of the board;

??Improper assembly due to BGA balls or pins of the IC not soldered properly and don't come in contact with pads on the board;

??Crosstalk between the signals due to proximity, thus hampering connectivity at higher frequencies;

??Signal integrity issues due to long trace lengths and inadequate termination.

Please view the PDF document for more information.

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