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Rambus, Cadence partner on verified PCIe solutions

Posted: 06 Sep 2007 ?? ?Print Version ?Bookmark and Share

Keywords:verified PCle solution? verification? PCI Express?

Rambus Inc. and Cadence Design Systems Inc. have collaborated to develop fully integrated and independently verified PCI Express (PCIe) solutions.

The result of the joint work provides designers with an independently verified solution that seamlessly integrates Rambus' design IP with the automated verification IP from Cadence. This solution helps shorten time-to-market with an efficient, predictable, and low-risk SoC design and verification to enhance the quality of the end product.

In addition, the solution includes the Cadence Compliance Management System (CMS) featuring a PCIe compliance verification plan and compliance tests, both of which have been specifically customized to the Rambus design IP. The CMS provides an automated plan and metric-driven solution to reach high levels of coverage without the need to develop tests. Based on the Cadence Incisive Plan-to-Closure methodology, the offering allows customers to maximize design quality while minimizing protocol expertise and verification time.

"This solution leverages the strengths of both companies, speeding up the IP integration process and increasing productivity and quality for customers," said Steve Glaser, VP of marketing at Cadence's verification division. "Designers will gain a higher degree of predictability with the functional coverage provided by the Rambus design-IP-specific CMS. The result gives our mutual customers confidence that they will get to market on schedule with a quality product."

"Increasingly powerful computing and consumer electronics applications require IP solutions that are flexible and seamlessly integrate into our customers' designs," said Tim Messegee, VP of marketing at Rambus Inc. "With this collaboration, Cadence and Rambus continue our commitment to provide the market with superior integrated IP and EDA solutions that accelerate time to market and reduce design risk."




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