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Single-chip JPEG2000 encoder, decoder roll out

Posted: 12 Sep 2007 ?? ?Print Version ?Bookmark and Share

Keywords:JPEG2000 encoder and decoder? JPEG2000 cores?

At the International Broadcasting Convention (IBC) on Sept. 7, Xilinx Inc. and Barco Silex have unveiled their jointly developed single-chip JPEG2000 encoder and decoder solutions.

Based on the success of Barco Silex JPEG2000 cores on Xilinx Virtex-5 FPGAs, the solutions significantly reduce the cost of broadcast and digital cinema initiative (DCI) archiving, post-production, distribution and server systems.

The encoder chip solution allows the creation of a single board capable of real-time encoding performance, which previously required a cluster of PCs or application specific standard products (ASSPs). The encoder and decoder solutions sustain the high encoding requirements of DCI formats including 2,048 x 1,080 and 4,096 x 2,160 resolutions with up to 48fps, and broadcast formats including 1,080i and 1,080p. The decoder chip solution replaces up to 12 separate ASSP chips. System developers further benefit from the capacity and flexibility of Xilinx Virtex-5 FPGAs with the ability to add encryption or watermarking functionality.

"Our success in implementing JPEG2000 cores on Xilinx Virtex-5 FPGAs provides the broadcast and digital cinema industry with access to JPEG2000 board solutions, offering a unique combination of high-performance (real-time HD or DCI) and cost-effective programmability," said Frederic Devisch, sales and marketing manager, Barco Silex.

The Barco Silex JPEG2000 hardware cores are immediately available for third party licensing.

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