Formal verification fetches better results

Feist: Complete formal verification is not a silver bullet for all functional verification tasks.

Functional verification is a severe bottleneck in SoC projects, with a significant impact on time-to-market, competitiveness and profitability. It involves two major tasks: First, ensuring that the SoC's modules and intellectual property (IP) operate as expected, and second, ensuring that the interaction of these building blocks delivers the required chip-level functionality.

Advanced simulation-based verification is and will remain the primary chip-level verification workhorse for the foreseeable future. But what about module-level verification, which accounts for up to 70 percent of the total verification effort? Using established verification approaches, can we answer this fundamental question: Can I be absolutely sure that my module/IP behaves as expected for all possible input scenarios?

The short answer is no.

The EDA industry has attempted to address this high-risk situation with a plethora of incremental advances to simulation-based verification. Despite these advances, functional verification complexity, effort and costs are growing; tool productivity gains are failing to keep pace with increasing design complexity; and the error escape rate shows no sign of abating. As a result, redesign and respin rates remain stubbornly high.

Equivalence checking
But is this a reason for despair? Not really. Look at what happened to synthesis verification a decade ago. At that time, gate-level simulation was replaced by a new formal verification approach: equivalence checking. Although a paradigm shift requiring new tools, methodologies and skills, equivalence checking was adopted because it proved to deliver far superior results.

What equivalence checking did for synthesis verification a decade ago, complete formal functional verification can do for digital modules and IP today. It is a one-tool, one-methodology, one-workstation solution. It delivers 2x to 5x higher productivity than a thorough simulation-based verification, and its completeness ensures 100 percent input scenario coverage and 100 percent output behavior coverage. It leaves no doubt that the module will behave as expected—always. It delivers a true functional sign-off. And this was the original promise of formal verification.

Complete formal verification is not a silver bullet for all functional verification tasks. But for a broad range of digital modules and IP, it delivers far superior results in terms of verification quality, effort and costs.

IP companies, SoC companies and the EDA industry can reverse the trends of recent years by adopting complete formal functional verification.

- Peter Feist
President and CEO, OneSpin Solutions GmbH