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High-k/metal-gate tools enhance 45nm designs

Posted: 17 Sep 2007 ?? ?Print Version ?Bookmark and Share

Keywords:high-k/metal-gate design? 45nm design tools? Centura Endura platform?

Applied Materials Inc. recently took a big step into the high-k/metal-gate arena by rolling out a trio of tools for advanced gate-stack and related applications at 45nm: an atomic-layer deposition (ALD) chamber for Applied's single-wafer Centura platform to enable advanced hafnium-based high-k dielectrics for logic and memory devices; various configurations for Applied's Endura platform, which enables the development of metal gates in transistor designs; and a post-etch tool, dubbed Carina, for high-k/metal-gate apps. The tools are designed to develop the two major gate-stack camps in the logic field: replacement gate and gate first.

Intel Corp. is reportedly developing replacement-gate technology at the 45nm node, while IBM Corp. is backing the gate-first scheme. The remaining gate-stack proposals, such as damascene flow, fully silicided and metal-inserted polysilicon stacks, are no longer considered mainstream solutions.

With the announcement, Applied is expanding its efforts in an emerging but fragmented ALD market that also counts ASM, Aviza, Genus, Hitachi Kokusai, IPS, Novellus, Tokyo Electron and Veeco as players. Applied fielded ALD tools for the niche-oriented copper/barrier seed market in 2002, but PHY-layer deposition has pushed out the need for ALD in that segment.

DRAM vendors such as Samsung and Hynix have used high-k dielectrics as a means to reduce the capacitor sizes in their shrinking memory designs. DRAM makers have used ALD to enable high-k films. Samsung and others are looking to develop next-generation NAND memory, based on a charge-trapped flash technology. Charge-trapped flash will also require high-k films, which in turn will require ALD.

For gate-stack applications in logic, silicon dioxide is running out of gas at the 45nm node, propelling the need for high-k and metal gates. Device makers such as AMD, IBM, Intel and NEC are moving into the high-k/metal-gate era at the 45nm node.

High-k development approaches for gate-stack applications include ALD and metal oxide chemical vapor deposition (MOCVD). Applied is said to offer both ALD and MOCVD for logic gate stacks.

MOCVD is geared for thicker films at 100-200?, while ALD is intended for structures below 50?, said Reza Arghavani, a fellow for the Thin Films Group at Applied.

To enable high-k and metal gates, Applied Materials is its existing Centura platform with a new high-k module; the existing Endura platform, tuned for metal gates; and the new Carina system for post-etch.

For ALD, the Centura platform consists of four modules: ALD, oxidation, nitridation and anneal. The company's ALD module supports films between 10? and 30?.

For metal gates, Applied Materials is offering various configurations in its Endura platform, depending on the requirements. In addition, the company rolled out the Carina post-etch module in its Centura platform.

"Key to the system's benchmark performance is high-temperature cathode," according to Applied Materials. "Processing at high temperatures produces smooth, vertical profiles without the high-k 'foot' and silicon recess that plague conventional-temperature alternatives."

- Mark LaPedus
EE Times

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