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Avoid design snags with silicon contour predictor

Posted: 17 Sep 2007 ?? ?Print Version ?Bookmark and Share

Keywords:design modification? DFM with silicon contour prediction? manufacturing technology?

The IC design implementation methodology has gone through several inflection points over the past few decades. We are currently at a point where designers need more predictability to offset the variations induced by manufacturing processes such as lithography and etch.

At 90nm and below, perfect squares and rectangles from GDSII patterns are converted into contours on silicon. Unfortunately, irrespective of how much optical proximity correction or resolution enhancement technology is applied to those ideal shapes, they turn into contours and thus change the characteristics of the active and passive layers of the chip. This variability then gets worse across the process window. Since design implementation and analysis is based on ideal GDSII shapes, there are substantial differences between the design stage and the actual wafer. The variation in performance increases with shrinking geometries.

The way to bring back predictability into a design and optimize for yield and performance is to deal with the variability by bringing silicon contours into the design stage and then analyzing the design for catastrophic and parametric failures. This is the foundation of a true design-for-manufacturing methodology.

Please view the PDF document for more information.

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