Programmable bridge offers low power, small footprint

Lattice Semiconductor Corp. is offering what it claims is the industry's lowest-power XAUI/HiGig/HiGig+ to SPI4.2 programmable Fabric Interface Chip (FIC) implemented in its LatticeSCM FPGAs.

This programmable bridge solution employs the LatticeSCM device's System Packet Interface Level 4 Phase 2 (SPI4.2) hard IP capability, and includes Lattice's 10GbE MAC soft IP core and the XAUI/HiGig/HiGig+ to SPI4.2 bridge design. By integrating these features, the bridge provides a high-performance interface between the Serdes-based XAUI standard, used ubiquitously in 10GbE networks, and SPI4.2, a popular parallel bus interface used by Network Processor Unit (NPU) devices.

When implemented in a LatticeSCM-15E FPGA packaged in a space-saving 256 fine pitch Ball Grid Array (fpBGA) package, the programmable bridge requires 17mm x 17mm on a PCB while consuming 2.5W of power.

In support of the bridge function, the LatticeSCM devices include from 4- to 32 channels of high-speed Serdes capable of supporting data rates from 600Mbps to 3.8Gbps. The flexiPCS Physical Coding Sublayer block embedded in the devices supports an array of popular communications data protocols, including Gigabit Ethernet, Fibre Channel, 10GbE (XAUI), PCIe, Serial RapidIO and SONET/SDH.

Pricing for the new device is $14,950. A XAUI to SPI4.2 IP bundle is downloadable by clicking here.

- Ismini Scouras
eeProductCenter