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Taiwan's MediaTek adopts Mentor's formal verification tech

Posted: 20 Sep 2007 ?? ?Print Version ?Bookmark and Share

Keywords:formal verification technology? verification flow? RTL?

Mentor Graphics Corp. announced that Taiwanese fabless IC firm MediaTek has selected the 0-In formal verification technology to make it an integral part of its verification flow for their next generation design projects.

Mentor's 0-In formal verification technology focuses on proving large sets of properties on large designs in the least amount of time and offers an intuitive graphical analysis and debug environment.

MediaTek's complex multimedia designs require thorough verification at the RTL level to confirm interface compliance and the functionality of control logic. MediaTek uses the 0-In formal verification technology for bug hunting, which is the process of pinpointing errors during functional verification and analyzing assertions that focus on verification hot spots.

"There is an evolution in designers' work that is moving towards increased verification requirements," said Robert Hum, VP and general manager of Mentor design verification and test division. "To address these needs, designers need to adopt early, aggressive formal methods to reduce design cycles and improve design quality. 0-In formal verification technology has a proven track record of delivering the capability, performance and features needed to complete this critical task."




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