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UMC taps Synopsys memory IP design tool

Posted: 21 Sep 2007 ?? ?Print Version ?Bookmark and Share

Keywords:memory IP development environment solution? 65nm? 45nm?

UMC has selected Synopsys Inc.'s memory IP development automation environment for its advanced design processes.

The Synopsys development environment is production-proven and allows designers to develop memories in less time and with fewer dedicated resources. The memory IP development environment solution includes three vital components that help reduce development time and also features integrated memory quality assurance (QA) system source code for all standard memory architectures and characterization utilities. The integrated memory QA system shortens development time by enabling production-ready memory releases. The available source code, which contains support for industry standard EDA views, enables short ramp-up times for engineers to provide high reliability memories. Moreover, the characterization utilities ensure efficient generation of accurate memory models.

"As part of UMC's SoC foundry solution strategy, we are seeking to further enhance our portfolio of memory IP to meet our customers' expanding requirements as they design into today's most advanced technologies," said Raymond Leung, vice president of memory IP development at UMC. "Synopsys' memory development automation environment is capable of developing memory IP solutions for 65nm and 45nm memories and cores. The combination of Synopsys' development environment, support and training, makes this a valuable EDA offering for meeting our customers' memory IP requirements."

Available today, the Synopsys' memory IP development software development environment includes separate software tools and implementation support.

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