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Magma, UMC deliver verification, DFM tools for 65nm

Posted: 24 Sep 2007 ?? ?Print Version ?Bookmark and Share

Keywords:65nm process? design rule checking? advanced modeling? processors?

Magma Design Automation Inc. has partnered with UMC to deliver a broad physical verification and design for manufacturability (DFM) solution for 65nm designs.

The two companies completed joint qualification of Magma's QuartzTM DRC, Quartz LVS and Quartz DFM for UMC's advanced processes and development of foundry-validated runsets and models that support the flow, which is tuned to detect design problems so they are corrected quickly. With the software, runsets and models, designers can accelerate time to market and improve manufacturability of chips targeted for UMC's advanced 65nm process technology.

Quartz DRC and Quartz LVS are said to be the industry's first fully scalable design rule checking (DRC) and layout vs. schematic (LVS) products. Leveraging a unique architecture and advanced modeling capabilities, this revolutionary physical verification solution allows affordable, massively distributed processing. With this technology and the right number of processors, virtually any design can be physically verified in less than 2hrs. Quartz DFM allows designers to analyze and characterize the timing and power impact due to sources of manufacturing variability, such as lithography and CMP. With this, designers can reduce the guard-banding required by traditional design flows, allowing significant gains in timing and power performance.

"UMC continually works to provide its customers with design and manufacturing solutions that help ensure silicon success. We believe Magma's physical verification software provides significant turnaround time advantages to our mutual customers," said Ken Liou, director of the Design Support division at UMC. "The qualification of Quartz DRC, Quartz LVS and Quartz DFM for our 65nm process and our ongoing collaboration with Magma demonstrates our commitment to helping our customers address complex system-on-chip design challenges and shorten their time to market."




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