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Firms collaborate to address 65nm FPGA design verification

Posted: 24 Sep 2007 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA design verification? 65nm? IP blocks? intellectual property?

Xilinx Inc. has teamed up with Cadence Design Systems Inc., Mentor Graphics Corp. and Synopsys Inc. to define and implement new verification flows to maximize productivity and quality of results for ultrahigh-density designs targeting today's 65nm FPGAs and new emerging FPGA architectures.

"With the growing complexity of today's 65nm FPGAs, verification has become a major time-consuming portion of the FPGA design flow," said Bruce Talley, VP of the design software division at Xilinx. "By collaborating with the industry's leading EDA providers, we can develop solutions to address the challenges faced by our customers at 65nm and beyond."

The collaboration will focus on expanding coverage, improving simulation runtime and reducing verification time in an environment that allows designers to achieve aggressive design goals. Major releases of these tools and methodologies are expected in the first half of 2008.

Ongoing growth trends in FPGA architecture present escalating challenges for logic designers with increasing density points and capabilities across a wide range of application domains. The companies will work together to build upon existing technologies to develop next-generation verification solutions, enabling system designers to streamline the verification process.

"Today, FPGA verification flows rival advanced verification flows for complex ASICs and SoCs," said Robert Hum, vice president and general manager of Mentor Graphics Design Verification and Test division. "A focused effort on verification will bring the latest technology such as assertions, transaction-level modeling, clock domain crossing, formal verification and others to the FPGA designer."

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