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Practical design considerations: Ethernet vs. RapidIO standards

Posted: 24 Sep 2007 ?? ?Print Version ?Bookmark and Share

Keywords:Ethernet? RapidIO? embedded design? practical design considerations?

Tom Cox
RapidIO Trade Association

Engineers often discover ways to leverage technology in applications for which it was never intended. Sometimes the fit is "good enough" and the resulting economies of scale are sufficient to make the extended technology implementation successful. But the desire to use a familiar technology runs the risk of stretching the technology beyond its capabilities, complicating designs and creating unforeseen problems.

For example, Ethernet is frequently considered a prime candidate for the convergence protocol in system-level fabrics, yet comparing the familiar Ethernet to the RapidIO specification for board- and chassis-level applications can be surprising.

Design hurdles
Ethernet was designed for large networks with many endpoints, each with a powerful processor available for protocol stack processing. RapidIO technology was designed specifically for embedded in-the-box and chassis control plane applications, and emphasizes reliability with minimal latency, limited software dependence, protocol extensibility, and simplified switching that provides effective data rates from 667Mbps to 30Gbps. Moreover, RapidIO technology features hardware-based protocol processing, support for read/write operations, messaging, data streaming, HWQoS, data plane extensions and protocol encapsulation.

Ethernet is supported by a wide range of Layer 3 and higher protocols that implement optional and advanced functionality, expanding Ethernet's scope in the network while introducing various derivative protocol definitions without unified specification. This results in significantly increased stack complexity to accommodate the variations, leading to higher costs for processing resources and higher packet latency.

Another challenge for Ethernet is how and when protocol offload engines will be standardized in the embedded industry, as there is no standard driver-level interface for hardware off-load. Every off-load implementation is proprietary, each with a proprietary Ethernet stack, which locks OEMs into one option for future designs.

The RapidIO specification outlines the baseline functionality for chassis- and board-level applications, resulting in lower implementation costs and reduced overall complexity. Since most of the RapidIO protocol is implemented in hardware, its software drivers are simpler than the typical Ethernet TCP/IP stack. RapidIO stacks can depend upon the existence and consistency of standardized implementations.

Design factors
Large packets compensate for Ethernet's high overhead in LAN and WAN applications; limited flow control makes switches less complex throughout the network, and the ability to drop packets provides efficient congestion management. These characteristics, advantageous for LANs, can be devastating in chassis- and board-level control plane applications. Because control plane transactions are limited in size, high overhead reduces efficiency. For example, the TCP/IP header alone adds 40bytes.

The RapidIO specification optimizes header size to maximize efficiency for packets typically used in control plane applications. The RapidIO protocol provides robust flow control and guaranteed delivery?both essential for maintaining the priority and reliability of control plane transactions?providing fabric usage in complex topologies in excess of 50 percent. Link-level error correction minimizes latency jitter, while minimizing or eliminating software stacks at endpoints substantially lowers end-to-end latency.

Implementing Ethernet to support control plane applications that are unable to tolerate packet loss requires significant over-provisioning, typically 25 to 35 percent, depending on a system's traffic demands. While over-provisioning reduces end-to-end latency and latency jitter, it decimates throughput: at 25 percent usage, the sustainable effective throughput of Layer 2 traffic for GbE is about 250Mbps and only 2.5G for 10GbE, depending upon average packet size.

Power considerations
Both Ethernet and RapidIO interconnect utilize the power efficiencies of a single-lane XAUI-like PHY interface, which dissipates anywhere from 70mW to 200mW at 3.125Gbaud. For Ethernet applications using 1000Base-T PHYs, power dissipation rises to between 640 mW and 950mW.

Ethernet protocol processing can consume more power compared to a RapidIO-based endpoint, because most Ethernet implementations run a software stack on a high-frequency host processor. Applying the rule of thumb that a Hz of CPU clock rate is required per bit of terminated TCP/IP performance, the power to terminate a line-rate GbE link includes a GHz-class processor (adding on the order of watts of power) in addition to that consumed by the Gigabit PHY.

RapidIO protocol processing is implemented in hardware; however, one RapidIO endpoint (including messaging support) is only 25 percent larger than a Gigabit Ethernet controller, but without a full a TCP/IP off-load engine [TOE], on the same processor. With a complete TOE, the Ethernet controller would be comparable to or larger than the RapidIO controller. When considering PHY cost and size, both Ethernet and RapidIO systems can utilize a XAUI-like PHY, suggesting comparable silicon complexity and areas between the two standards.

Ethernet endpoints for backplane applications require specialized functionality, such as VLAN QoS support, that significantly reduces the number of applicable applications, eliminating high volume advantages. Additionally, Ethernet's best price economies today are for 4 to 8 port switches, not the highly aggregated configurations required for efficient backplane configurations.

Price is also impacted by existing silicon and the ecosystem. For an application such as a 12 to 24 port ATCA-like backplane, an Ethernet controller requires both VLAN QoS and SERDES PHYs. The necessary devices are offered by a limited number of vendors. A comparable RapidIO device is readily available due to its standardized nature, contributing to a more competitive marketplace.

Effective throughput
When the aforementioned factors are taken into account, RapidIO technology offers 2.5 times more bandwidth per link than Gigabit Ethernet. The difference is more pronounced when fabric bandwidth requirements exceed 1 Gbps. In these cases, the only Ethernet option is 10 Gbps, which may introduce undesirable over-provisioning costs without performance benefits. RapidIO devices offer higher effective bandwidth for payloads less than 1024 bytes at lower costs, without the added expense and complexity associated with managing Ethernet stack processing at 10 Gbps.

While the ability to consolidate interconnect levels by bringing Ethernet down to the chassis and board level exists, the complexities arising from its derivatives, associated inefficiencies, lower throughput and smaller ecosystem make Ethernet less appealing for use as a backplane or control plane technology. The RapidIO protocol, designed from its inception to serve in chassis- and board-level applications, offers the efficiency of a hardware-based protocol processing architecture, superior throughput without extreme over-provisioning, lower overhead, more reliable flow control, more efficient power usage, and a well-established ecosystem. RapidIO-based implementations can consolidate higher levels of the system-level interconnect more efficiently and reliably than Ethernet, making RapidIO the technology of choice for next-generation high-speed, embedded applications.

About the author
Tom Cox
is the executive director of the RapidIO Trade Association.

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