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Drive parametric yields higher at 65nm, beyond

Posted: 01 Oct 2007 ?? ?Print Version ?Bookmark and Share

Keywords:parametric yield characterization? within-die variability? measurement resolution? design rules?

Yield ramp has historically been the fab's burden. The yield-ramp cycle was cleanly partitioned into three phases: process development, pilot production and volume production. Designers slept well when using a process qualified for production, knowing that as long as their designs obeyed the rules, good yields would result.

With today's sub-100nm process technologies, however, the fab often discovers that parametric and systematic yield issues creep into volume production.

The fab is attempting to address such yield fallout through more complex design rules and guidelines that will hopefully capture the variety of clever layout choices designers may make. But the effective application of more complex rules and guidelines requires more sophisticated analysis tools not yet available. Lacking such tools, the fab may opt to mitigate the emergence of new yield-limiting mechanisms by imposing greater restrictions on the choices that designers can make. Such restrictions may create area penalties that dilute the benefits of adopting the new process technology.

A framework that allows manufacturers and designers to collaborate well is critically needed to address these new process-design interactions. Such a framework must first supply characterization solutions for obtaining the data necessary for both process and design yield improvement.

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