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Perform power sequencing with PMUs

Posted: 16 Oct 2007 ?? ?Print Version ?Bookmark and Share

Keywords:power sequencing with PMUs? avoid latch-up? working multiple voltage rail?

Power sequencing is an important topic to consider when working with multiple voltage rail environments. Many devices require timing and voltage differences during power up and down, such as in DSPs, FPGAs, ASICs and microprocessors.

To fully exploit the potential of power management devices such as National Semiconductor's LP3906 and LP3907, which provide programmable delays in power sequencing, system designers should understand their systems' power supply sequencing needs. Before we explore the capabilities of chips that provide power management tools to the system designer, we need to know the critical issues of device operation and long term reliability.

Designing a system without proper power sequencing may compromise reliability and damage ESD protection in the system, especially when some blocks are powered before other blocks. Cumulative exposure to this condition shortens the chip's usable lifetime and can even contribute to electrical latch-up. This occurs when voltage and current levels increate beyond the normal stress operating levels of the device. This is especially important with peripheral devices such as data converters and memory, which need specific power timing sequences.

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