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Cadence, Mentor unify SystemVerilog method

Posted: 16 Oct 2007 ?? ?Print Version ?Bookmark and Share

Keywords:hardware description language? SystemVerilog? OVM? AVM?

Cadence Design Systems Inc. and Mentor Graphics Corp. have joined forces to promote a common approach to the verification of design files based on SystemVerilog. The Open Verification Methodology (OVM), available under an Apache Version 2.0 open-source license, is a superset of a previous Cadence approach, called URM, and Mentor's previous approach, called AVM. Dennis Brophy, director of business development at Mentor, and Steve Glaser, corporate VP of verification marketing at Cadence, said that OVM will deliver portability of files and interoperability with any simulator supporting the IEEE 1800 SystemVerilog standard. Moreover, it extends verification intellectual property by allowing for containment of code blocks and clustering to provide support of block-to-chip-to-system hierarchy and reuse while supporting descriptions at the transaction and register-transfer levels of abstraction (TLM and RTL).

"People use other languages for design?SystemC is a good example?and we need to support SystemC and SystemVerilog working together at the TLM as well as the RTL," said Glaser.

OVM reduces the complexity of adopting SystemVerilog by embedding verification practices into its methodology and library, the companies stated. Its class library is available in source code format and supported by documentation, tips, examples and code fragments outlining the method of use. The class library uses SystemVerilog and runs on any compliant simulator, providing building blocks (objects) for verification environments and a common set of low-level utilities.

OVM and the library "are appealing to our broad verification IP customer base, and we will foster the transition to OVM through our existing support for SystemVerilog and AVM," Sanjay Srivastava, president and CEO of Denali Software Inc., said.

Robert Hurley, CEO of Doulos Ltd, hailed "the commitment from Cadence and Mentor to offer an open verification methodology rooted in IEEE 1800 with transaction-level modeling support that is interoperable among EDA tools and that supports interoperable VIP."

A preliminary class library release started shipping to selected customers in September. A production release is scheduled in Q4.

- Peter Clarke
EE Times Europe




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