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IMEC extends CMOS scaling research to DRAM MIMCAP

Posted: 17 Oct 2007 ?? ?Print Version ?Bookmark and Share

Keywords:CMOS scaling? DRAM MIMCAP? 45nm node?

IMEC announced it has initiated a research on next-generation DRAM metal-insulator-metal capacitors (MIMCAP) process technology as part of its (sub-)32nm CMOS device scaling program.

The research will enable IMEC and its partners to address the material and integration requirements to scale DRAM MIMCAP to future technology generations. The added focus follows an earlier extension of its traditional logic- and SRAM-oriented program with a DRAM periphery transistor sub-program in November 2006. The objective of the latter sub-program is to research high-k and metal gate options sustaining a DRAM-oriented process flow.

In order to scale DRAM towards the 50nm node and beyond, MIMCAP dielectrics require materials with a higher dielectric constant compared to current industrial materials such as ZrO2. By mid 2008, an effective oxide thickness of 0.5nm is targeted for the MIMCAP dielectric in the sub-50nm technology node, going down to 0.3nm in 2009 for the sub-45nm node. Scaling the dielectric equivalent oxide thickness while attaining very low leakage currents is one of the major bottlenecks DRAM industry is facing. Building on its expertise in high-k dielectrics and memory research, IMEC expands its CMOS device scaling program to address these challenges.

In the first phase, a baseline process for MIMCAP evaluation is set up based on TiN electrode and ZrO2 as the capacitor dielectric. This baseline process is used as a vehicle for screening new electrode materials such as W, Mo, TaC, Ru, etc. Next, new material stacks combining high-k and electrodes will be screened theoretically and experimentally for potential integration. The stringent DRAM specifications as dictated by the ITRS will be used as selection criteria. They include leakage current lower than 1fA/cell and a total physical MIM thickness smaller than 20nm. Finally, a MIMCAP deposition process will be developed looking at major integration issues and mimicking as much as possible the effect of full DRAM integration such as passivation, anneal, etc. MIMCAP test structures will be integrated and characterized on electrical and reliability performance.

Both metal-organic chemical vapor deposition and atomic-layer deposition will be used since they allow depositing high-quality thin films.

The DRAM MIMCAP sub-program is part of the CMOS device scaling program within IMEC's (sub-)32nm CMOS research platform. The platform brings the top five memory suppliers together with the top leading logic IDMs and foundries including Elpida, Hynix, Infineon/Qimonda, Intel, Micron, NXP, Panasonic, Samsung, STMicroelectronics, Texas Instruments and TSMC.

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