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ARM launches Cortex-A9 multiprocessor

Posted: 18 Oct 2007 ?? ?Print Version ?Bookmark and Share

Keywords:Cortex-A9? processor? symmetric multiprocessing?

ARM has unveiled its latest processor architecture at its own ARM Developers Conference which took place in Santa Clara, California, early this month.

The Cortex-A9 comes in single-core form with roughly the equivalent performance of the established Cortex-A8 processor. However it is also available with two, three or four cores clustered together to provide up to and beyond 8,000 dhrystone Mips of symmetric multiprocessing (SMP) performance. The core is synthesizable and is expected to be capable of clocking at in excess of 1GHz in a leading edge process, although the greatest power efficiencies will come as clocks are slowed or cores switched off.

ARM also announced that several companies have already licensed Cortex-A9 processor cores including NEC Electronics, NVidia, Samsung, STMicroelectronics and Texas Instruments.

There's no silicon as yet and the deliverables from IP licensor ARM to its partners will not be finalized until Q1 2008, according to John Goodacre, multiprocessing program manager for ARM. So although the cores are available for licensing immediately, developers could use ARM's first multiprocessor corethe ARM11 MPcore processor. This has been in silicon for a couple of years, is supported by the OpenMP compiler technology from KTH Royal Institute of Technology of Sweden and by a number of OS vendors. It also pioneered the use of such features as 'Adaptive Shutdown' and Intelligent Energy Manager technology. However, the core was based on ARMv6 instruction set architecture.

ARM has now brought multiprocessing and these other ARM11 MPcore benefits to its ARMv7 architecture and is aiming the scalable architecture at demanding applications in the home, such as HDTV STBs and home server engines, and on the move, in the form of mobile Internet handsets.

Refined architecture
The A9 processing core itself is a refinement of the Cortex-A8. "There are a couple of extra instructions in support of multiprocessing, but it is backward compatible," said Goodacre.

Like the A8, it is superscalar with a multi-issue 8-stage pipeline. Early branch resolution is evaluated asynchronously to instruction fetch and it allows continuous fetch and decode of two instructions per clock cycle. However, the A9 core pipeline goes further than its predecessor does by supporting out-of-order instruction dispatch and completion.

The new architecture handles up to four processors per cluster and adds to ARM's multiprocessor capability with an Accelerator Coherence Port (ACP) supporting hardware accelerators and DMA units, support for TrustZone technology with interrupt virtualization and a Generalized Interrupt Controller (GIC).

As a fully fledged ARMv7 device the A9 MPcore supports Thumb2 instructions, TrustZone, a floating-point unit and Neon, ARM's single instruction multiple data (SIMD) extension in support of streaming media processing. In addition the architecture is scalable beyond four cores. "Licensees can put down more than one cluster on a chip if they want," said Goodacre.

The instruction and data L1 caches associated with each processing core incorporate cache-coherency support that's synchronized via the snoop control unit (SCU). A local coherence bus links these to the SCU. And in a break with tradition the A9 is being offered as a synthesizable core from the start. "It's synthesizable and configurable, in terms of FPU or Neon additions to the processor, cache size, interrupt scheme, and interface," said Goodacre.

IP for licensing
Even though ARM has not finalized the design the company is licensing it. "We have delivered 'beta' [design files] to licensees. Q1 next year is sign-off from ARM." That would suggest that those licensees could take another year to 18 months to get their silicon made. "I would expect the first devices [using the Cortex-A9] on the shelves of Vodafone at the end of 2009 and volume in 2010," said Goodacre. It is also expected that the design, currently being benchmarked against 65-nm design files will debut in 45nm silicon.

But who are the operating system partners?

Symmetric multiprocessing is not a problem, said Goodacre. While declining to name A9 processor partners Goodacre refered to the companies that have successfully got reference implementations running on the ARM11 MPcore, including Nucleus from Mentor Graphics, the generic Linux kernel, QNX, Mobilinux from MontaVista Software Inc. and Japan's eSol Co. Ltd. which has ported a blended asymmetric and symmetric multiprocessing (AMP/SMP) operating system. "Symbian isn't officially supporting multiprocessing on ARM11 but they have it running in the lab," said Goodacre.

That list of supporters gives some indications of where Goodacre and ARM expect the A9 MPcore to be deployed with the mobile Internet being a key battleground to be fought over.

Goodacre divided the application space up into a number of segments, most of which won't require the more than 8000DMips of performance on offer from the A9 MPcore.

Low, medium and high-end versions of next-generation Internet-connected handsets will need up to 900-, 1,500- and 3,000 DMips, respectively, Goodacre asserted. For most devices a single-core A9 will do, while the top end would be best served by a two- or three-core A9 processor.

User-interactive consumer devices in the home cover a similar performance range although up to four cores could be deployed. The application that is likely to be most demanding, and best able to use the scalability of multiprocessing are home gateways, Goodacre said.

- Peter Clarke
EE Times Europe

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