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Rambus memory controller runs at 1,600MHz

Posted: 19 Oct 2007 ?? ?Print Version ?Bookmark and Share

Keywords:DDR3? DDR2? DRAM? memory controller?

Rambus Inc. has introduced its memory controller interface solution for DDR3 DRAM at this week's Rambus Developer Forum in Taiwan. The fully integrated hard macro cell provides the PHY interface between the controller logic and DDR3 or DDR2 DRAM devices for data rates of up to 1,600MHz.

Optimized for low power and reduced silicon area, the Rambus DDR3 memory controller interface cell is designed to accommodate a broad range of applications including PC main memory, consumer electronics, servers, workstations, and network communications. To serve these applications, Rambus has architected and developed a DDR3 memory controller interface macro-cell that engineers can seamlessly integrate into their customer owned tooling (COT) or ASIC chip.

"As signaling frequencies of mainstream DDR DRAMs continue to increase, the memory interfaces critical to system performance have become very challenging to design," said Martin Scott, senior VP of engineering at Rambus. "Using our extensive signal integrity experience, we have architected a low-risk, highly optimized DDR3 memory controller interface that meets the performance requirements of both main memory and consumer applications."

To ensure first-silicon success, a reliable system environment for high-volume production, and rapid in-system qualification, the Rambus DDR3 interface solution incorporates Rambus innovations. These include FlexPhase timing adjustment circuits for precise on-chip data alignment with the clock, calibrated output drivers, on-die termination and LabStation software environment for bring-up, characterization and validation of the DDR3 interface in the end-user application.

Other key interface features include 800-1,600MHz data rates, support for DDR3 and DDR2 signaling modes, on-chip phase-locked loop (PLL), on-chip delay-locked loop (DLL) and levelization support for fly-by command and address architecture. The device also boasts of the Rambus FlexPhase based in-PHY module that provides characterization and testing capability in the production system. Additional features include multi-drop bus and multi-rank module support for large capacity systems and variable data bit-widths (8/16/32/64bit) with optional ECC support

Rambus DDR cells are supported by comprehensive system design and integration services that include a complete set of design models and integration tools, including GDSII database, timing models, layout verification netlists, gate-level models, place-and-route outline and placement guidelines. Package design and system board layout services are also available.

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