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32Mbit SDRAM design cuts cost of SiPs for handsets

Posted: 23 Oct 2007 ?? ?Print Version ?Bookmark and Share

Keywords:DRAM? 32Mbit SDRAM? system-in-package?

Inapac Technology Inc., a provider of IP-based DRAM solutions for system-in-package (SiP) and multichip-package (MCP) devices, has rolled out a new 32Mbit SDRAM design to its family of products.

The new 32Mbit SDRAM design is characterized for production on the ProMOS Technology Inc.'s 0.12?m manufacturing process.

IP-based provider Inapac estimates that the total cost of incorporating the 32Mbit DRAM die into a SiP/MCP solution will be less than 60 cents in volume production in 2008.

''This new 32Mbit design makes it easier and more cost-efficient to create SiPs for a new generation of mobile handset applications,'' said Naresh Baliga, VP of marketing for Inapac.

The chip design is based on Inapac's SiPFLOW platform, which incorporates a design-for-test (DFT) architecture and production methodology that enables SiP/MCP suppliers to minimize costs, according to the firm.

Samples for the new IP are available now, along with the full suite of Inapac's SiPFLOW platform deliverables.

- Mark LaPedus
EE Times

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