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India researchers push new design methodology

Posted: 26 Oct 2007 ?? ?Print Version ?Bookmark and Share

Keywords:India researchers? design methodology? ILS architecture?

Researchers from the Indian Institute of Technology together with another institute in Kolkata have proposed a layout-aware, coverage-driven technique for Illinois Scan Architecture (ILS) used to cut test application time and test data volume in high-density circuits.

The researchers, S. Banerjee, D.R. Chowdhury and B.B. Bhattacharya, said they proposed the new methodology to improve fault coverage while greatly reducing the scan wire length. Experimental results on different benchmark circuits have shown the versatility of their proposed technique, they claimed.

To achieve high fault coverage using the ILS architecture, judicious grouping and ordering of scan flip-flops is needed for selecting those segments. This information increases wiring complexity and cost of the scan chain, since the physical locations of the flip-flops on silicon are determined at an early design stage before scan insertion.

The researchers instead proposed a layout-aware approach as well as coverage-driven ILS design, where partitioning flip-flops into ILS segments is determined by their geometric locations. Meanwhile, the set of flip-flops to be placed in parallel is determined by the minimum incompatibility relations among the corresponding bits of a test data to enhance fault coverage in broadcast mode. Consequently, this reduces the number of test patterns required in serial mode.

"Our proposed methodology reduces test application time significantly, and at the same time, achieves high fault coverage," the researchers said. "Switching power dissipation in the scan cells can be reduced by further reordering of groups in the segments. The method also allows the user to choose the number of segments required to achieve desired wiring cost, test application time and fault coverage."

Their proposed layout-aware design of the ILS architecture accounts for the physical locations of the flip-flops and provides a compromise between fault coverage, test application time/test data volume and wiring cost.

- K.C. Krishnadas
EE Times

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