Intel exec calls for advanced test tools for next-gen SoC

In his talk at the opening of last week's International Test Conference, Gadi Singer, Intel Corp. VP and assistant general manager, stressed the need to improve test development tools for next-generation SoC.

In the plenary "Meeting the Challenges at the Extreme Ends of the Spectrum—Nanotechnology and Giga Complexity," Singer noted that MIPS per cubic foot, or MIPS per pound, has been increasing by a factor of 100 every 10 years since 1940. Although the exponential changes have been on a smooth curve, there have been many discontinuities and inflection points over that time.

"Now, four diverse trends are extending the envelope in all directions," said Singer. First, IC complexity and diversity are being driven by the emergence of smart (portable) devices. These new designs include more complex cores, multiple processing engines, increased memories, specialized subsystems and multiple communications SoC. In addition, Singer said that "the 'Internet effect' shows the effect of convergence of digital data into all functions, and requires an increase in hardware and software interactions."

Improved tools, techniques
Obviously, the testing challenges for this next-generation SoC require improvements in test development tools and techniques, Singer said. Scan has a speed issue and is becoming access limited. Functional test has insufficient automation and no standards. Built-in self-test (BIST) is pattern limited for memories, and logic BIST is area expensive. The only way to improve this situation is to have an integrated design for x methodology—where x is test, manufacturing, yield and reliability—coupled with extreme modularity for plug-and-play design and reconfigurable and adaptable test solutions for all IP blocks.

Second, power and performance are moving toward a lower, fixed budget. "Next-generation chips," he added, "will need to show increased performance within a constant power envelope, and design variants will have to fit into different power budgets." Test for power and screening for performance at a power level will become essential. Unfortunately, the industry needs more solutions than what is currently available, because the testing will have to address power testing, at-speed power testing, and at-workload testing as factors in battery life.

The third area is nanotechnology. Moore's law is likely to continue for the foreseeable future, even though as much innovation will be in materials as in scaling. "Even more innovation is needed in the test space," Singer said. Scaling leads to increased transistors and functions per die, while also causing increases in intra- and inter-die variability. Future designs will demand increased sensitivity to variations at design and test, while IP must be tolerant of manufacturing variability. Singer noted, "Adaptive test methods will be required to address the variability and resulting design sensitivities."

Cutting turnaround time
Finally, all this challenging work must now be done in less time, Singer said. "The total turnaround time is the key metric in moving from design to prototype to production. The short product windows will require late binding—deciding on the details of implementation at the last minute in the design cycle." Design is seriously challenging the test development capabilities. The industry needs fast and affordable test development capabilities to enable late-stage reconfiguration."

- Tets Maniwa
EE Times