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Customizable MCUs take on FPGA tasks

Posted: 01 Nov 2007 ?? ?Print Version ?Bookmark and Share

Keywords:customizable MCU with MPCF? FPGA design? IP content?

Today's product life cycles can be as short as six months. This situation makes it impossible to achieve the cost, power and performance benefits of custom ASICs. The custom ASIC's design cycleusually about a yearis often longer than the life of the end product. On top of that, standard cell ASICs can have NRE costs anywhere from $300,000 for a bare bones 0.13?m design to over $1M for a 90nm design with sophisticated IP content. They are not economically viable if unit volumes are under about 100,000 units a year.

Platform or structured ASICs with pre-designed IP blocks and programmable ASIC gates were developed to reduce costs and design time. This approach cuts the design cycle from a year or more to several months and also reduces NREs to around $150,000. However, the larger feature sizes associated with gate arrays make their unit costs too high to offset the NREs.

It is usually faster and more cost-effective to implement designs in standard off-the-shelf MCUs, many of which are SoCs that offer extensive networking capability and human interface functions, such as LCD controllers and camera interfaces. These off-the-shelf SoCs frequently have all the functionality with performance and low power consumption that could be achieved with a cell-based ASIC.

All too often, however, a computationally intensive portion of the design requires hardware acceleration. Turbocoding, GPS correlators and graphics processing are all candidates for implementation in hardware. Increasingly, these DSP-type functions are being implemented in FPGAs, which have seen such rapid price declines due to shrinking process technologies that they have replaced platform ASICs.

View the PDF document for more information.




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