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Processor battle moves to the cores

Posted: 01 Nov 2007 ?? ?Print Version ?Bookmark and Share

Keywords:processor cores? 45nm node? Intel-AMD battle?

The latest maneuvers in the chess match between Advanced Micro Devices Inc. (AMD) and Intel Corp. find the rivals advancing toward similar architectures. That leaves AMD in a difficult spot, because it trails Intel by an entire process node in silicon technology. There are enough moves ahead that no endgame is at hand, but it's not looking good for AMD.

By next year, Intel will ship its first server processors with integrated memory controllers and a new high-speed interconnect, matching what AMD has been offering for a few years. By sometime in 2009, both companies will have graphics, and possibly, cores for security or Ethernet networking on their processors as well.

Intel will have an edge in performance, power and cost because it will deliver its parts in 45nm technology, with an eye on the 32nm node. AMD's parts will be mainly in 65nm technology, moving to 45nm.

SoC convert
In the course of playing this game, the world's biggest semiconductor company has become an SoC convert. At September's Intel Developer Forum (IDF), Intel discussed at least four SoC designs it has in the works for markets ranging from handheld gadgets to high-end visualization systems.

How the new SoC dynamics play out in the traditional X86 contest remains to be seen, with several key questions still unanswered. Will Intel's new QuickPath processor interconnect have an edge in raw technology or time-to-market over AMD's HyperTransport? Will either company do a better job of gathering around itself a robust group of coprocessor makers that may be future SoC partners? Perhaps most important, who will make the more effective moves in the emerging game of identifying markets and creating the right mix of cores in a microprocessor to address them?

"The next 18 months will be pretty interesting," said Dean McCarron, principal of Mercury Research. The question, he said, is how the integrated devices handle the transition from graphics and other cores that are resident in chipsets to cores that are contained in the CPUs. "A lot of it depends on the market segmentation," he said.

Both companies seem to recognize that putting a processor and a graphics core on a single die for thin and light notebooks is a big win. In 2009, AMD will release Falcon, a notebook CPU and the first of its Fusion CPUs with on-board graphics. Intel has confirmed it also will put its CPUs and graphics into a single package in 2009, using its 45nm process.

Eyeing notebooks
The notebook is a key target because it is on course to become the biggest slice of the computer market measured in units by 2009, exceeding desktops, according to Intel. AMD had a slight edge in incorporating graphics because of the topnotch graphics cores it acquired with ATI Technologies last year. But Intel has blunted that edge, announcing plans to migrate from 90nm to 32nm process technology for its graphics cores by 2010.

"We are the No. 1 supplier of PC graphics through our integrated chipset products today, and we've been using silicon technology that's one or two generations behind the state-of-the-art," Intel CEO Paul Otellini said in his IDF keynote. "We're changing that pace starting next year."

Intel's Otellini holds Penryn wafer, based on 45nm high-k metal-gate process.

Servers are likely to follow the pattern set by Sun Microsystems, putting Ethernet MACs and crypto accelerators on the die rather than integrating graphics. Desktops will likely carve out a middle ground.

AMD and Intel will compete to define and serve a variety of market segments in these broader sectors. Both companies are laying the foundation for new, core-based design processes.

Otellini said Intel's second-generation 45nm chipsetthe Nehalem familysports a dynamic, modular architecture that can be readily configured for different cores and caches.

Intel has grouped previously separate server, desktop and notebook CPU design teams into larger groups charged with designing a handful of broad architectures and derivatives. It pulled out some engineers to create SoC designs, said Stephen Smith, operations manager for Intel's Digital Enterprise Group.

Intel now has separate SoC designs in the works for consumer gear, network accelerators (Tolapai), high-end visualization systems (Larabee) and handhelds (Silverthorne). Most of the new products will ship or be demonstrated for the first time in 2008. Otellini said the consumer CPU will include an A/V pipeline block and will be shown at the Consumer Electronics Show in January.

The Larabee high-end visualization chip includes an array of x86 cores sharing a single cache and using a familiar x86 programming model. "Larabee is more like an experiment or a calculated risk in a new area for Intel," McCarron said, in a comment that might well have applied to all of the new SoCs.

The Tolapai device houses an x86 core along with a security accelerator, memory controller and various I/O interfaces. It aims to power a rising tide of networking appliances used in small- and midsized-business networks.

New interconnect
Intel announced plans at IDF to put an improved interconnect, called QuickPath, in its computer CPUs starting with the Nehalem family debuting in the fall of 2008, but it provided few details on the new link.

David Kanter, editor of the Real World Technologies Website, compiled an extensive analysis of QuickPath based on his reading of Intel patents on the technology. He concluded it runs at 4.8- to 6.4GHz and offers links up to 20bits wide.

By contrast, AMD's HyperTransport 3.0 is a 32bit-wide bus, but its maximum speed is only 5.2GHz. Moreover, it won't appear on all AMD chips until sometime in 2009.

"AMD could be in serious trouble for six to 12 months," depending on the exact timing of bus upgrades and chip rollouts, Kanter said.

AMD's Hector Ruiz girds for bus war as Intel rolls QuickPath.

"We think Intel will have a performance advantage with QuickPath," said Richard Doherty, principal of market watcher Envisioneering Group. "I don't think they have all their figures of merit ready, but it looks good, and I don't think AMD can match it. It seems a better balance in bandwidth and latency than the AMD approach."

Intel and AMD are also competing to convince third parties with cards and co-processors to hop on their separate I/O buses. AMD is licensing a cache-coherent version of HyperTransport to such companies. Intel is licensing QuickPath to select companies, but it is recommending that most customers use Geneseo, its proposal for PCIe 3.0 that has some of the features but not all the complexity of a coherent bus, and thus, is easier and cheaper to implement.

"Ninety-five percent of the apps benefit from being on a bus like this," said Ajay Bhatt, chief I/O architect at Intel. The PCI Special Interest Group is rallying around the Geneseo proposal as a likely candidate for its PCIe 3.0 standard, Bhatt added.

Intel wants the PCIe standard to be adopted broadly because it helps simplify much of its software design. Even silicon blocks on Intel chipsets and processors often use PCI software semantics, although they ride a wider and faster proprietary on-die interconnect, Bhatt said.

Eric Lemoine, chief architect of Tarari agreed that the PCIe and Geneseo approach is the simplest for linking his chips with X86 hosts. He added, however, that the HyperTransport bus represents a better architecture.

"With HyperTransport, you can access and work at the level of the cache lines, and it offers low latency," he said.

Geneseo is a decent approach, but Lemoine said an even simpler way forward could come from making some adjustments to existing memory and I/O controllers. Today's PCIe parts typically don't return full 512byte requests and don't relay data in sequential orderdetails that significantly slow the workings of a high-performance accelerator, he added.

Process edge
Some Wall Street analysts, including Steven Eliscu of UBS Securities LLC, said AMD is under a serious long-term threat from Intel's process technology advantage. The process lead will help Intel maintain an edge in frequencies, cost and power, he said. Thus, AMD may gain market share and see rising average selling prices over the next year, but beyond that it will be hard for the company to maintain its position, Eliscu said.

At IDF, Intel showed working versions of server, desktop and notebook processors using its 45nm technology. The company said it would release about a dozen of the Penryn family CPUs in November and more in 2008.

Intel's high-k dielectric is a key part of that process. "Others have announced 45nm, but none have hafnium-based dielectrics. We will be unique in this technology in the industry," said Otellini.

The Intel CEO also showed a 32nm test wafer comprised of working 291Mbit SRAMs, each sporting 1.9 billion transistors. "This gives us the confidence to build mainstream microprocessors on this technology a short two years from today," he said.

Intel has set itself a demanding schedule of introducing a process technology every two years. It's a pace that AMD, which shipped its first 65nm processors only in Septembersix months later than promisedwill find hard to match.

For its part, Intel expects it will ship more 45nm than 65nm parts by next fall. "We have sent qualification samples of 45nm server and high-end desktop processors to customers for their final qualifications," said Smith.

- Rick Merritt
EE Times

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