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45nm designs demand efficient floorplans

Posted: 01 Nov 2007 ?? ?Print Version ?Bookmark and Share

Keywords:I/O planning? 45nm design? efficient floor plans?

With the move to the 45nm process node, more chip designs are going to be pad-limited, and die sizes will be directly affected by how I/Os are placed and sequenced efficiently.

While this is an impending technology crisis, most of the focus on 45nm issues today is within the intellectual property (IP) core area of the chip, because that is where the technology will be implemented. But these new cores will have to live in a world where higher voltages, larger geometries and standard interfaces still hold sway.

With the migration to 45nm cores, optimized I/O planning and placement will become even more critical. These challenges beg the question: Who should take charge of a chip's I/O plan along with the considerations for the package and the rest of the system?

I/O plan
Unlike the internal workings of the IP core, I/Os will not shrink to 45nm technology for several reasons. Although new 45nm cores have smaller geometries and can therefore operate at lower voltages, I/Os must deal with other devices in the system that are not 45nm designs and must still handle higher voltages.

I/Os must be robust so as not to be compromised by higher switching voltages. Most I/Os in use today are developed by third-party vendors, not necessarily by the company designing the 45nm core. These IP providers typically do not live on the cutting edge of process nodes and thus lag in releasing new libraries.

In addition, it takes significant time and effort to design and characterize I/Os. Compounding the challenge are companies that do not want to be the first ones to use next-generation I/Os, because those elements have not been fully battle-tested.

Finally, Serdes transceivers are self-contained macros that can include analog circuitry. Serdes are huge compared with other I/Os, and their size impacts I/O planning and placement. Other circuits and I/Os must be efficiently placed around Serdes blocks.

High-speed Serdes networks require specific placement with respect to how devices will fit within the rest of the system. As a result, it is critical to consider system requirements when placing Serdes blocks. This system- or PCB-driven flow is a critical element for successful implementation of high-speed networks.

To combat the challenges, differential pairs are increasingly being used. Differential circuits require specific I/O placement and planning to assure proper routing on package and board. The unmistakable conclusion is that methodologies to support system-level I/O planning are a must for 45nm implementation.

Cost reduction
Three types of designs are being migrated to 45nm: design implemented for cost reduction, completely new designs and next-generation designs to meet designers' specific challenges.

Reducing the core and die sizes help reduce cost, but can result in a pad-limited design. The I/O can restrict the amount of die reduction that can take place. Thus, to take full advantage of the new technology, the I/O plan needs to be redesigned for better efficiency.

In most cases of technology migration for cost reduction, the package or board will not be changed. That means the new I/O plan must reuse the existing package ball-out and the existing core requirements. The only way to successfully reuse the existing package or board is to have a methodology that can honor constraints from both sides. Successful implementation makes the most efficient use of the die area while honoring reuse requirements.

In a new design, the goal is to add functionality. Here, the original core is reduced in size, and circuitry is added. With more circuitry comes more I/O. Furthermore, there may still be a reuse element on the package or board side. The challenge is to implement the new circuitry while honoring any reuse constraints. Those constraints may be a predefined Serdes placement, differential-pair ball-out or existing analog circuitry. The methodology must build a new I/O plan around the existing circuitry and constraints.

Next-generation 45nm design issues are significant. At lower voltages, power/ground I/O planning is more important than ever. Circuitry is more susceptible to cross-coupling. If the chip and package are not planned as a single circuit, cross-coupling with the package can severely affect the chip's performance. This happens when routing on the package passes under the chip. Completely forbidding routing under a flip-chip die is not practical, however, and could drive up package cost. Again, these factors must be accounted for from the start to avoid issues down the road. A denser die equals more I/O, which equals more package balls, which equals denser PCB routing. That makes board-driven I/O planning a must to control cost and realize optimal performance.

Packaging guidance
Designers migrating to 45nm don't have to be packaging experts, but they need design tools that offer packaging guidance. One scenario gaining acceptance is to implement an emerging chip design methodology known as package-aware chip design. Just as floor planning is a critical component of SoC design, package-aware I/O planning can help meet cost/performance and time-to-market pressures. I/O planning minimizes die size through optimized I/O and bump placement. An early I/O and package plan gives designers a way to analyze the interconnect from the chip's I/O buffers to the PCB.

With this new methodology, I/O planning is done early in the design flowduring the prototype phase and before floor planning, when changes can be more easily implemented. The trade-offs can be made in such a way that the chip's performance is not affected and a routable I/O plan can be established to meet cost targets.

By introducing automated I/O planning early in the design cycle, I/O performance is enhanced for signal integrity, power integrity, physical implementation and low cost. Designers can optimize I/O placement to reduce die size or fully utilize the die area. They can use the least expensive package technology while ensuring that performance targets are met, with accurate estimates of load conditions to determine driver strength requirements. Perhaps most useful, designers can manage chip and package connectivity within the design environment, rather than doing so externally via a spreadsheet.

Package engineers, for their part, will be able to use the information to create an initial package layout. I/O planning, as part of this methodology, offers a departure from the typical sequential design of chip and package to one that's concurrent and enables a "one pass" design flow where multiple iterations are avoided.

Unified data model
At its foundation is a single, unified data model to support the chip and package as active components in a single user interface. The model serves as the repository of the "golden" chip and package interconnect matrix where chip and package connectivity can be managed. Its capabilities include chip and package trade-off exploration with a feedback metric that details electrical and physical constraints. The data model facilitates the optimization process by bringing all design elements into the synthesis flow through the use of the industry-standard OpenAccess database.

Unified data model facilitates the optimization process. Design elements are part of synthesis flow via OpenAccess database.

Features of a package-aware chip design methodology include I/O synthesis, placement and routing. I/O synthesis creates an optimized I/O plan with cost-effective packaging options while satisfying physical and electrical constraints. A correct-by-design I/O ring is created to satisfy a set of constraints that include signal/power/ground requirements, package design rules, the core floor plan and board-level I/O.

Synthesis calculates the current requirements for a particular voltage plane based on driver models and calculates the number of balls required. It must accommodate each power domain for designs with multiple voltage domains. Synthesis must also be able to optimize the I/O ring plan for minimum die size and I/O row area. If the die size is fixed, it will succeed only if a feasible I/O ring plan exists for the given die size.

I/Os, bumps or bond pads and pins are placed around the periphery of the die by a placement engine before synthesis. The engine considers preplaced instances (I/O and/or the IP core), groupings of I/O cells (bus I/Os, for example) and electrical constraints. Once the I/O ring has been synthesized, it generates a legal I/O placement.

Of course, a consideration before implementation is how a methodology such as this will work in an existing design flow. The answer is the need to support industry standard formats such the Library Exchange Format/Design Exchange format (LEF/DEF) on the chip side and Automatic Data Processing on the package side. The software used to implement the methodology must be able to operate in a planning environment where all data may not be present and the design may be incomplete. Therefore, the extraction, analysis and verification tools must be flexible and smart enough to account for such limitations while providing results that are accurate enough to be useful.

Also, package-level routing and voltage-domain plane cutting need to be design rule check clean and must abide by packaging rulesan important consideration for establishing valid chip-to-package net assignments and proper power plane bump/ball assignments.

- Joel McGrath
Technical Marketing Manager
Rio Design Automation Inc.

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