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Addressing the issues of process node transition

Posted: 01 Nov 2007 ?? ?Print Version ?Bookmark and Share

Keywords:process node? 45nm design? tool methodology process performance?

Through the move to smaller process geometries, related market opportunities and cost pressures have driven cycle time for process development and adoption in different directions. While time-to-market pressures require process availability and driver projects to be implemented earlier than ever, the increased cost of node development requires design teams to maximize the use of a given process node as long as possible.

These two opposing vectors require increasing overlap of node development and longer-term support of manufacturing nodes. As a result, we face an ever-shrinking time window between manufacturing process development (node availability); design and manufacturing infrastructure creation (node readiness); and adoption of the techniques, methodology and tools for 45nm designs (node adoption).

In the transition to 45nm, reaching node availability, readiness and adoption has become significantly more complex. Influencing factors include increased design and design analysis complexity; the establishment of multiple sourcing manufacturing qualifications; and the many pressures to keep 45nm lifecycle times the same as those of previous nodes.

Minimize challenges
Texas Instruments' multidisciplinary teams partnered with driver customers and external suppliers to enable 45nm process design techniques for the company and its customers in preparation for the 45nm adoption. TI chip designers have been using 45nm technology and found this transition more difficult than with the 65nm process generation.

To minimize some of the challenges ahead, a heightened effort is required to develop tools and methodology to meet process power/performance and area entitlement from node to node. Engaging early with multiple EDA vendors to drive development allows solutions to be in place for design at the right time, even if this is ahead of the bulk of primary short-term revenue for EDA vendors and also speculative development in some cases.

Engineering efforts for 45nm node availability, readiness and adoption were faced with the primary challenges of designing with increasing variation and DFM tools.

Increasing variation
Variation falls into two primary categories: random and systematic. Both are important, and require methodology and flows to be in place. Tools and solutions can vary based on different levels of design!from transistor and circuit level to IP-block and onto full-chip assembly. Digital logic, memory and analog designs can also have different requirements and approaches to variation methodology.

To address random variation, transistor-level statistical Spice models, simulation and optimization are now commonly used. Statistical or variation-aware extraction, characterization and statistical static timing analysis are handling random variation at gate and chip level. In some cases, design methodology provides low effort avoidance or correct-by-construction strategies. Several tools are now maturing in this area. Implementation and deployment are bringing new challenges in use models and signoff correlation.

Systematic variation can be handled with new tools and models, including chemical-mechanical planarization, smart fill, litho contours, shape-based extraction, stress, temperature and many others. These tools fill the gaps and mitigate the need for many more design corners or excessive uncertainty margin. Avoidance methodology can also be included. Designers should avoid the loss of context-free gate-level abstraction or have solutions that maintain the productivity lift from abstraction. This issue challenges the core of traditional ASIC methodology and EDA toolsets.


In the transition to 45nm, reaching node availability, readiness and adoption are significantly more complex than ever before based upon increased design and design analysis complexity.
(Click to view image.)

DFM tools
They can help address lithography limits, optical proximity correction and resolution enhancement techniques (RET). The balance between restrictive design rules and massive use of design-for-manufacturing (DFM) or technology computer-aided design tools, however, is an emerging issue that requires a lot of attention to get right. The main risks include excessive area, power on one side, and massive compute and analysis cycle times on the other. (It can also lead to failed silicon if a component is missing from the analysis or models.)

Rule-based checkers!The ability of traditional rule-based checkers to validate layout has been breaking down for several nodes now. Lithography and process simulation model-based hotspot checkers are being used to augment traditional checking. Still, tool capacity is an ongoing concern.

Scaling!Maintaining power, performance and area scaling is a major challenge. Some physical and material fundamentals are slowing down scaling of critical parameters such as Lgate and Tox. Wire resistance is becoming more dominant, and metal stacks cannot reverse scale further and remain competitive. This drives process enhancement and changes on the design side, sometimes all the way back to system architecture.

Power management!TI has been developing and introducing new techniques with every process generation for handheld power management. A large toolkit of techniques, tools and methodology is needed, further complicating the design process. Examples include clock gating, multi-Vdd/islands, Multi-Vt, adaptive voltage and frequency scaling, multiple sleep modes, bias techniques, power gating and so forth. In 45nm, even non-handheld design teams have to seriously look at power management techniques for both active and static power.

There are many design specific parameters (e.g. activity rate, voltage supplies, temperature envelope and system architecture) that change the balance of which techniques to apply and how aggressive to be in order to find the minimum energy yet preserve cost targets and system performance levels. This implies close architect/logic design/physical design interaction and optimization are required.

Complexity!The sheer volume of transistors included on these very complex 45nm SoC is a challenge for both capacity and tool cycle times. Capabilities such as true incremental tools, multinode distributed processing, stricter hierarchical system design and ESL are now becoming critical. Human (manual) floorplanning of 400 or more memories, 40M gates and multiple analog blocks is becoming infeasible, and automation tools in this area are immature. The capacity trend also magnifies the introduction costs of new analysis tools, additional corners or sign-off closure loops.

Despite the challenges, the industry is progressing with 45nm design. By working together, we're addressing the issues with continued innovation for the transition into this process generation and beyond. This is what smart engineering is all about.

- Mike Fazeli,Worldwide EDA Strategy Manager
Clive Bittlestone, TI Fellow
Texas Instruments Inc.

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