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EDA/IP??

Dealing with IP at 65nm and below

Posted: 01 Nov 2007 ?? ?Print Version ?Bookmark and Share

Keywords:analog mixed/signal circuits? sub-micron CMOS technology? 45nm process node?

The demand for connectivity intellectual property (IP) for high-speed serial buses such as USB 2.0, PCI Express, serial ATA, DDR2 and HDMI is increasing. This is because these standard interfaces are included in SoCs designed for applications such as single-chip recordable DVD codecs and MP3 players.

To stretch the battery life of these SoCs, the semiconductor technologies require ultralow-power derivatives of high-performance logic manufacturing processes that enable production of very low-power SoCs for these mobile platforms and small form-factor devices. Today, many of these SoCs are manufactured in the 90nm process node, and the ramp up for 65nm design starts has been more aggressive than expected. The 45nm process design is following close behind, with early versions of design rules and process parameters already available.

The challenge from the IP provider's viewpoint is to meet analog performance in a technology that has been targeted for densely packed digital logic. From the SoC integrator's perspective, the IP should be easy to integrate. The IP provider should have already dealt with all of the details of creating the IP. The IP should also incorporate new circuit design techniques that accommodate lower supply voltages necessary for portable systems. At the smaller process nodes, design-for-manufacturing (DFM) must also be considered.

I/O devices
Reduced supply voltages mean that architectures that once worked at 3.3V or 2.5V now need to work at 1.8V or lower without any loss in performance. One way to address this is to use a mixture of high-voltage I/O devices with the lower-voltage core devices. In addition, all the post processing to support DFM requirements increases the performance variation in these devices. This is due to effects like shallow-trench isolation (STI) induced stress (NMOS becomes slower and the PMOS faster.), nwell proximity effects, contact stress and phase shift mask correction algorithms. There is also a time-dependent variation due to negative bias temperature instability (NBTI) in PMOS devices and hot carrier injection (HCI) in NMOS devices.

Performance can be maintained at 90-, 65- and even at 45nm by using a mixture of I/O and core devices. The trick is to know where and how to use them, which is where the expertise of the IP provider comes in. For analog circuits operating at higher supply voltages, high voltage-tolerant transistors can be used to replace the standard transistors that can only reliably operate up to nominal supply voltages.

The figure illustrates three examples using I/O transistors that can typically operate at higher supply voltages. These transistors enable direct reuse of most circuit architectures running at supply voltages corresponding to the original design but are high supply voltages compared with the nominal supply voltage of the CMOS process used. These structures are adequate for ESD protection, but more exotic protection schemes are needed for embedded analog functions.

The easiest way to design with high supply voltages is to use the commonly available thick-oxide transistor (Figure example a) that is comparable to a two-generation-old standard transistor. To benefit from technology scaling, however, you need to use compound structures that have thin-oxide transistors (Figure examples b and c) which typically outperform the thick-oxide transistor (Figure example a) in matching noise and output impedance. These compound structures have some disadvantages: They are asymmetric, do not solve gate-leakage issues and require suitable cascade voltages at power-up.

These I/O transistors are examples of devices that can operate at higher supply voltage levels.

Careful selection of the analog sections to run at high supply voltages and the best type of transistor (thin oxide, thick oxide or compound) will circumvent one of the main roadblocks in 65nm CMOS technologies!the low nominal supply voltage. Note that thick-oxide transistors also solve gate-leakage issues as their gate leakage is usually negligible.

More processing steps
To meet DFM demands, additional processing steps are required. These are also sources that add variation in devices and thus adversely impact IP performance:

  • STI!A fabrication method used to isolate active areas, STI can cause currents to be different from simulation. It depends on transistor location.

  • NBTI!It degrades PMOS devices progressively over time by an increase in the threshold voltage (Vth) and reduction in mobility due to negative gate bias and/or higher temperatures, usually around 100<C. The net effect is that the PMOS current drive is degraded over time. This can induce timing failures in digital circuits modeled as a Vth shift.

  • Matched devices!They are asymmetrically stressed (e.g. current mirrors and differential pairs) and will have an additional mismatch component besides mismatch from process variations, causing additional system performance degradation.

  • HCI!It degrades the performance of NMOS devices in a similar way, but through a different physical mechanism to NBTI. Unlike NBTI, HCI is a function of the electric field across the channel; NBTI degradation is a function of the field across the oxide modeled as an Idsat shift.

These effects do have a serious impact on the design of the analog/mixed-signal portions of the connectivity IP, and the vendor must have deep expertise in understanding these effects and including them as automated simulation tools.

Circuit layout must also be able to well accommodate proximity effects. Advanced extraction decks include STI/nwell proximity effects. However, these are only back-annotated after layout is complete. Layout immune methodology helps bridge the gap between schematic simulations and extracted simulation results.

Chip integration
From the SoC integrator's perspective, the IP vendor should also provide all the views for chip floor planning and integration, integration of the analog/mixed-signal in the SoC and the SoC on the board!i.e. LEF and Spice models of the I/Os. The IP should also have no special requirements for guarding combinations or distances between the IP and the intended SoC.

Other important considerations are that the analog/mixed-signal IP is designed in a standard CMOS digital process. There are no process options required such as deep nwell, or on-chip inductors or varactors.

Thorough testing
Since IP providers often don't know where customers will place the IP, they must thoroughly test the noise rejection of the IP in their test chips. They should mimic a very noisy SoC environment!both substrate and supply!when they perform jitter measurements.

Testing becomes a real issue with high-speed analog/mixed-signal designs. It's important to ensure maximum fault coverage with minimum test time. It's impractical to spend 30s on the tester, so the IP should contain hooks to allow the production test engineer to test the IP without adding to the test time budget. The SoC designers do not design the IP and thus cannot add test features. If they cannot simulate it with a test bench, they cannot test it. Additional issues that the test engineer faces include:

  • SoC test engineers usually have vectors they stream in/out from simulation. All analog tests have to be hand coded.

  • Test engineers have to devise tests to get acceptable analog fault coverage. The designers do not know much about the analog portion of the IP.

  • Most analog tests require external hardware to properly test. Setting up this hardware takes time.

Hence, the IP vendor needs to provide the appropriate test vectors and IP test features that address these testing challenges.

- Navraj Nandra
Director of Marketing Mixed-Signal IP
Synopsys Inc.




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