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FPGA-based dev't platform eases migration to structured ASICs

Posted: 01 Nov 2007 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA? ASIC? development board?

An FPGA-based development platform that provides a seamless migration path to structured ASICs has been launched by TrellisWare Technologies Inc.

Based on Altera's Stratix II FPGAs, TrellisWare Technologies' new RapidFire development board enables fast prototyping and testing of complex PHY designs. The development board hosts two Stratix II FPGAs, thereby providing a high-density solution rich in logic and RAM blocks that can be used for the hardware acceleration of advanced commercial and military communication architectures. It allows customers to target either a Stratix II FPGA or a pin- and package-compatible HardCopy II structured ASIC solution for production. The board also allows customers to evaluate TrellisWare's full range of waveform, high-speed modem, and forward error correction (FEC) intellectual property (IP) products. In addition, RapidFire enables evaluation of TrellisWare's Chameleon, a powerful, low-power FEC ASIC, which implements TrellisWare's Flexible Low Density Parity Check (F-LDPC) technology.

Through the RapidFire environment, customers can develop, test and prototype advanced military communications systems, and seamlessly implement their design into either a Stratix II FPGA or HardCopy II structured ASIC. By scaling their completed designs to a HardCopy II structured ASIC, customers can gain a size, weight and power (SWaP) advantage.

Altera and TrellisWare will demonstrate the RapidFire development board in Altera's booth 1430 at MILCOM 2007 held in Orlando, Fla., October 29 through 31. The demonstration will include an F-LDPC implementation in Stratix II FPGAs, which will encode and decode a very high-throughput data stream (up to 1Gbps) with injected noise. For more information about the TrellisWare RapidFire development board, visit

- Clive Maxfield
EE Times Europe

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