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SPI host controller offers low pin count option

Posted: 05 Nov 2007 ?? ?Print Version ?Bookmark and Share

Keywords:serial peripheral interface? host controller?

QuickLogic Corp. has announced the addition of an SPI host controller to its customer specific standard product (CSSP) functional library. The SPI interface gives mobile device designers a low pin-count alternative to secure digital input output (SDIO) or mini-PCI for a high speed connection to wireless modules and other popular peripheral functions.

"QuickLogic's CSSP design approach is all about giving the OEM/ODM developers choices within a standard framework," said Brian Faith, QuickLogic's vice president, Solution Marketing. "The addition of the high speed SPI Host Controller to our silicon proven, system block library extends the developers' range of alternatives for connecting to high-performance peripherals such as Wi-Fi and GPS chipsets."

Today's wireless chipsets provide different host interfaces including SDIO, SPI and mini-PCI, which are the most widely used. Implemented in QuickLogic's platform products, an SDIO host controller requires 15 customizable building blocks (CBBs), and PCI requires 6 to 9 CBBs depending on the configuration. The SPI host controller requires only 3 CBBs and 4 I/Os, freeing CSSP resources for the implementation of additional functions. It is high speed and capable of operating at clock speeds to 52MHz. The SPI software driver provided by QuickLogic has low overhead and can be customized for specific peripherals for higher performance.

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