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Imagination unrolls Meta HTP multithreaded processor

Posted: 06 Nov 2007 ?? ?Print Version ?Bookmark and Share

Keywords:multithreading? virtual processors? SRAM? multiprocessing?

Multimedia processor licensor Imagination Technologies Group plc has announced Meta HTP, an implementation of the second generation of its multithreading Meta processor architecture.

The Meta multithreading architecture has been behind a lot of Imagination's processor core introductions over the last several years.

The Meta HTP architecture, based on the Meta2 architecture, extends support for different operating systems and should allow for faster processing speed, the company said in a statement.

Imagination's multithreading architecture allows for the overlapped execution of multiple threads, which is an approach that can minimize data dependencies, stalls and no-op cycles. As a result multiple time-critical applications and nonreal-time general purpose tasks can run concurrently on the same processor as if running on multiple virtual processors. Imagination claimed that one Meta HTP processor can replace multiple high performance RISC and DSP cores, thereby saving silicon die area and power consumption.

Refined, improved
Among the changes in the Meta HTP is that it implements a "longer pipeline" but Imagination did not say what they are comparing Meta HTP against. Nonetheless this pipeline would enable Meta HTP to achieve clock frequencies of ranging from 360MHz in a 130nm manufacturing process to 500MHz in 90nm and up to 700MHz in a 65nm process using standard cells together with high speed SRAM macros for cache.

A longer pipeline would normally reduce benchmark performance per MHz; however, META HTP includes additional architectural features to compensate including a return address cache and branch prediction table support. A four-threaded Meta HTP can deliver up to 1,552 dhrystone MIPS in a 65nm process.

The pipeline can be implemented with integer and optional floating point math capability that supports both 32bit single-precision and 64bit double-precision formats. Processors based on the Meta HTP core are code compatible with earlier Meta processors but can also introduced a 16bit instruction-set called Minim, which is similar in purpose to ARM's Thumb and Thumb2 short-format instruction sets. Minim increases code density by typically 20 to 30 percent relative to the regular 32bit instruction set, Imagination claimed.

Software creation follows the same development flow of a traditional processor with Meta HTP supported by Imagination's Codescape development tools.

Intgrated solution
As with previous Meta-based cores the multiple hardware threads within Meta HTP are each a virtual processor operating in a parallel overlapped manner with no context switching overheads, according to Imagination claims. Each thread can be a RISC style processing flow or a DSP style flow, which is decided during processor synthesis, and each virtual processor can run an independent OS, including Embedded Linux, Nucleus or Imagination_s own MeOS RTOS or they can run code natively.

"Meta HTP's scalable architecture has all the benefits of multiprocessing but with less silicon resource and development complexity. And it is significantly lower cost than a multiprocessor approach," said Tony King-Smith, VP of marketing at Imagination, in a statement. "Its unified architecture delivers both powerful DSP and general-purpose processing whilst the multithreading 'hides' memory latency in SoC solutions. Our customers have proven the benefits of the Meta architecture in millions of shipping devices; Meta HTP takes that to a new level of performance whilst maximizing the benefits of using multithreading with tightly integrated peripherals and co-processors in next generation SoCs."

Power management features include low-level clock gating, thread and resource scheduling to control clock gating operation and unused resources which are automatically 'switched off' cycle by cycle.

The Meta HTP is capable of up to four 16bit multiply-accumulate operations per cycle, or two 32bit MACs/cycle with a VLIW-like instruction template for complex DSP operations, combining four instructions in a single cycle. It features four-way set associative data and instruction caches and a thread-aware MMU able to support demand page virtual memory, as required by full featured OS, and optimized for Linux. Alongside the launch of Meta HTP, Imagination has also released a version of its Meta ATP multi-threaded processor core, which is based on the older Meta1 instructions set architecture. The latest release of Meta ATP includes a series of enhancements including core code memory and real time trace support.

- Peter Clarke
EE Times Europe

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