Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > Controls/MCUs
?
?
Controls/MCUs??

Tensilica unwraps 'smallest' 32bit processor core

Posted: 09 Nov 2007 ?? ?Print Version ?Bookmark and Share

Keywords:32bit processor core? SoC designs? 90nm? EDA tools?

Tensilica Inc. says it has released the industry's smallest licensable 32bit processor core based on an industry-standard architecture. The Diamond Standard 106Micro core occupies 0.26mm? in a 130nm G process and 0.13mm? in a 90nm G process, which makes it smaller than the ARM7 or Cortex-M3 cores, and at 1.22 Dhrystone Mips/MHz, it delivers higher performance than the ARM9E cores, said Tensilica.

The low-power Diamond Standard 106Micro is designed for simple controller applications in SoC designs, and is suitable for designers migrating from 8bit and 16bit MCUs to 32bit processors. All Diamond Standard processors are supported by an optimized set of Diamond Standard software tools and a wide range of industry infrastructure partners, who provide support with operating systems, design services, hardware prototyping and emulation, libraries and memories, EDA tools and peripherals, said Tensilica.

The Diamond Standard 106Micro is an extremely low power, cache-less controller. It uses a 5-stage pipeline so it can easily achieve 250MHz in 130G process and up to 400MHz in 90G process technology. By modelessly switching between 24bit and 16bit narrow instructions, it achieves a higher code density than other 32/16bit architectures, according to the company.

The Diamond 106Micro features separate local, tightly coupled, instruction and data RAMs to eliminate memory contention and to provide fast performance on performance-critical code and interrupt handling routines. RAM size is user selectable up to 128Kbytes. Other features include a 32bit iterative multiplier for arithmetic operations, a trace port for debug, an integrated timer, and an interrupt architecture with 15 interrupts at two priority levels for flexible and fast interrupt handling.

All Tensilica Diamond Series cores are available with the native high-performance Tensilica PIF processor interface, suitable for bridging to any on-chip bus (like OCP, CoreConnect). Designers can also use the ARM AXI interface or the AMBA AHB-Lite interface to leverage existing infrastructure and peripheral component sets.

The Diamond Standard 106Micro is available now.

- Gina Roos
eeProductCenter




Article Comments - Tensilica unwraps 'smallest' 32bit p...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top