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Synopsys, UMC co-develop 65nm reference flow

Posted: 09 Nov 2007 ?? ?Print Version ?Bookmark and Share

Keywords:reference design flow? collaboration? verification solution?

Synopsys Inc. and United Microelectronics Corp. (UMC) have co-developed a 65nm hierarchical, multi-voltage RTL-to-GDSII reference design flow.

The reference flow is derived from Synopsys' Pilot Design Environment and was developed by UMC and Synopsys Professional Services. The reference flow uses Synopsys' technology-leading Galaxy Design Platform including the Design Compiler Ultra synthesis solution, IC Compiler place-and-route solution, DFT MAX test solution, JupiterXT floorplanning solution, PrimeRail rail analysis solution, PrimeTime sign-off solution, Star-RCXT extraction solution, Hercules PVS physical verification solution, and TetraMAX ATPG solution.

The reference flow also utilizes Synopsys' Design Compiler Ultra topographical synthesis engine, enabling engineers to accurately predict chip performance results such as timing, area, testability and power consumption during logic synthesis. Using this engine, engineers can evaluate the chip and make early-stage modifications to provide a better starting point for physical implementation, reduce or even eliminate iterations between synthesis and physical implementation, and accelerate the design cycle.

"Our goal is to help customers increase their ability to achieve first-pass silicon success," said Stephen Fu, deputy director of the IP and design support division at UMC. "Our ongoing collaboration with Synopsys has helped us develop this validated 65nm reference flow and we expect this will help reduce design risk, lower power consumption, and reduce turnaround time for our customers."

Synopsys Professional Services and UMC engineers validated the reference flow using the test chip tape-out for "Leon," an open-source 32bit RISC microprocessor core. The test chip was partitioned into multiple voltage regions using the advanced, low-power reference flow. UMC also utilized its own internally developed library for its 65nm design process. The resulting test chip is highly configurable and expandable with additional digital and analog/mixed-signal intellectual property.

"As technology nodes become more complex, our strategic partnerships with world-class foundries like UMC are vital to help customers solve power management and yield challenges," said Rich Goldman, VP of strategic market development at Synopsys. "Through our collaboration with UMC, we now have a validated 65-nm reference flow that helps engineers to meet their design schedules and incorporates manufacturing technology for improved yield."

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