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Test system targets multiple memory MCP devices

Posted: 12 Nov 2007 ?? ?Print Version ?Bookmark and Share

Keywords:memory test system? tester-per-site architecture? multichip packages?

A high-speed, high-throughput memory test system for multichip packages (MCPs) has been introduced by Advantest Corp. The T5781 test system offers test speeds of 533Mbit/s for next-generation MCP devices that combine multiple memory types, including NAND, NOR and DRAM, in a single package.

Complementing the T5781 is the T5781 Engineering Station which is designed for device evaluation and test program development in a developmental/laboratory environment.

The memory test system tests speeds of up to 266MHz/533Mbit/s in DDR mode. Advantest designed the T5781/T5781ES to incorporate functions to test all memory types in an MCP on a single test system.

The test systems employ a tester-per-site architecture to efficiently test NAND flash memory. With test resources at each test site, including power sources and per-pin logic and algorithmic pattern generator functionality, devices can be individually controlled and tested. By making the test functions independent through tester-per-site architecture, the test time for NAND and SPI flash memory is reduced.

- Ismini Scouras
eeProductCenter




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