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Estimate power efficiently, effectively

Posted: 16 Nov 2007 ?? ?Print Version ?Bookmark and Share

Keywords:power reduction techniques? power estimation? power design? power management?

Miller: Power reduction techniques can only be implemented if they are considered during the architecture phase of the design cycle.

Designers frequently turn to advanced power reduction techniques such as power shutoff (PSO) and multisupply-voltage (MSV) architectures to help reach power consumption targets in advanced technology nodes (90nm and below). Those techniques, however, can only be implemented if they are considered during the architecture phase of the design cycle.

Here are suggestions for estimating power early in a project, with minimal effort, while ensuring reasonable accuracy.

Determine your design's components of power consumption. The design team should plot the components of power consumption early on. This estimate can be quite simple and could even be done using a spreadsheet before any RTL is complete. The key is to learn which components are fixed by specification and which can be affected through power reduction techniques.

Estimating the ratio of leakage power to dynamic power for each component is also valuable so designers can select appropriate power reduction techniques. MSV and clock gating are effective in reducing dynamic power, while PSO is used to reduce leakage power.

When RTL becomes available, the designers can do an RTL power analysis even before the design is synthesized to technology gates. This analysis will not be as accurate as a gate-level analysis, but it will allow the designer to quickly explore the potential power savings achieved with a given technique. If the power analysis engine is integrated with the synthesis engine, the designer can also determine the effect of reduced voltage on design timing. The quick turnaround of RTL-based analysis lets the design team find the optimum power architecture early in the flow.

Use accurate switching-activity data. Obtaining accurate switching-activity data requires simulating test cases that faithfully model real system stimulus. In many design flows, however, such simulation is not available until late in the design cycle, if at all. The designer needs to use the most accurate data available at any given point in the design flow and revise his estimate as new data becomes available.

If switching-activity data is not available from simulation, designers should estimate the switching activity on the chip's primary inputs and apply that estimate within the power analysis tool.

Consider simulation mode when generating switching activities. A zero-delay gate-level simulation will not account for any natural glitching that occurs in combinatorial logic, so it will always result in an optimistic power calculation. If the design team insists on gate-level simulation for power analysis, use an SDF-delay-based gate-level simulation.

Use accurate wire modeling. Every designer knows about the inaccuracies of wire load models when it comes to timing closure. Yet, many design teams use a "zero" wire load model for synthesis. This will result in inaccurate power estimation. Use a reasonable wire load model or, better yet, one of the "physical based" wire modeling technologies available in today's synthesis tools.

Use libraries that represent the worst-case power. Synthesis is always done using worst-case timing libraries, but they do not represent the worst-case power. Dynamic power is usually the highest in fast conditions, which can be represented by the "best case" timing libraries.

- Brad Miller
Senior Technical Leader
Cadence Design Systems

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