Up close and personal with Intel's 45nm high-k guys

Mistry: I think we constantly try to be ahead of the industry in terms of CMOS technology. That is certainly our goal.

Intel Corp. started 2007 with a bang with a breakthrough in transistor design, one of the biggest advancements in 40 years. In fact, 45nm high-k then became one of the buzzwords early on as Intel drew first blood in its highly intense battle for processor supremacy.

Now, the company is on its way on ending the year on a high note as it speeds past other chipmakers who are still months away from having production-ready 45nm chips. Intel in November introduced the first members of its Penryn family, 16 45nm processors using the high-k dielectrics to control current leakage.

Amid all the hype surrounding this feat, three Intel researchers—Robert Chau, Intel Senior Fellow, technology and manufacturing group director, transistor research and nanotechnology; Kaizad Mistry, 45nm program manager, logic technology development, technology and manufacturing Group; and Tahir Ghani, Fellow TMG, Portland technology development director, transistor technology and integration—who were part of the team behind the 45nm high-k metal gate success talk about the highs and lows of the project and what motivated them to press on and move on to more challenging endeavors

EE Times Asia: Can you walk us through the discovery process of the high-k materials? How long did the whole process take and how tough was it?
Mistry: In the late 1990s, we realized that silicon dioxide is running out of steam so at that point we started a research effort on finding the appropriate hi-k dielectric material. This was started under Robert's group.

Chau: Yeah, we felt that we need to look at a high-k material with higher dielectric constant. We started looking at different materials for a number of years, before we zero in on a couple of materials.

How many materials where you considering then?
Chau: We were looking at multiple materials, a wide range actually.

Mistry: I think it is in the range of five to 15 different kinds of materials, different flavors of different high-k materials.

Ghani: I think during the research phase, around 2001 to early 2002, we began to see data that it is very difficult to integrate high-k with polysilicon gates which was historically used by the industry in the last 40 years. Therefore, at that time, Robert's group looked at a range of different metals.

There are two different types of transistors: PMOS and NMOS. So there were two different metals with different electrical requirements needed for MMC devices.

At that time, the number of metals Robert's team looked at was significantly more than the number of high-k materials being looked at that time.

Mistry: So we were looking between five to 15 different high-k materials, and then we realized that fundamentally high-k materials were not compatible with polysilicon gates, which was around the turn of the decade. So at that point we started to look at not just the high-k material, but the two independent metal gates materials that provided the right electrical properties for NMOS and PMOS and were compatible with whatever high-k materials we chose.

So it really became a choice of three separate materials that have to work together and that process of choosing the right metal gate material that we tried with five or more high-k materials.

Ghani: What you see here is high-k metal gate strain and other features, really highlighting the very innovative nature of this field, people who work in this area.

What were the priorities for the different teams involved in this project?
Mistry: The development team was focused on making strain silicon. The research team came up with strain silicon germanium idea prior to the high-k. The development team was really focused on taking that into manufacturing for 90nm tech and then 65nm, while the research team's focus was really on high-k.

How many teams were working on the project?
Mistry: We have a research/transistor group that Robert heads and at any given point in time they are looking at N plus two, N plus three and beyond.

So today, 45nm is entering production, they [Robert's team] are looking at 22nm and beyond.

Then we have a development team that is responsible for taking each of the technology node into production, and right now, the development team is wrapping up 45nm and looking into 32nm.

And then we have a period of overlap we call pathfinding. For a year, year-and-a-half, the research team and the development team work together to define the next generation. For example, the 32nm today is in that space where the research and development teams is one virtual team working together. So any given point in time we are working on ramping a production, active development of a technology, pathfinding with the research team and the research team by itself looking beyond 22nm.

When did you guys realize that you were into something?
Ghani: There was no single point actually. There were various stages and each stage has their own challenges.

Can you explain more about those stages?
Ghani: About 2003, Robert's team has shown for the first time materials system with good NMOS and PMOS devices on different wafers but good NMOS and PMOS devices with high-k material devices.

Mistry: Very important is that we knew they were all compatible.

Ghani: So that was a critical stage when we have both converging devices on both NMOS and PMOS, and at that time, around end of 2003, they started the pathfinding program to finalize what transistor field effect required for 45nm node.

Chau: I think we have of firepower to continue with Moore's Law.

During pathfinding program, we looked at this process of doing high-k metal gates, and we looked at another way of doing high-k metal gates.

Our main objective during the high-k metal gate project was first to put NMOS and PMOS on the same wafer so that we can have a full CMOS integration technology. That's one of the key milestones that was met mid-2004.

The next challenge is that we do not have one working transistor—what we have are million and millions of transistors that need to work and be fully functional. That was a huge challenge, and it was one of the significant challenges that we need to surmount before deciding whether high-k metal gate is indeed a manufacturable technology.

Another challenge was to make this high-k metal gate stack reliable.

There was also a time, around the end of 2004 that we showed initial data that indicated with effort that we could address these challenges, at least the yield challenge, and at that time, we took the risk and committed to high-k metal gate process for 45nm node.

What was the most frustrating moment?
Mistry: There were many of them actually [laughs]. You know as Tahir mentioned, it is one thing to make one or two transistors work, it is quite another to take that into high-volume manufacturing, and you have you know thousands, millions of transistors work almost on the die, almost all the time. So that process was very challenging, which involved hundreds of people at our R&D center here at Oregon —we have 600 PhDs from the best universities around the world, and it really took this hundreds of PhDs to work together to resolve many of these problems that came up along the way, whether it was integrating the NMOS and PMOS transistors on the same wafer, coming up ways to that, and then solving all the defect problems and process capabilities problem that originated when putting this law into practice.

Yeah, it was hard work, there were many sleepless nights, long days, hours for many people.

Ghani: What I think is important to this organization was that once we committed to high-k metal gates it was the whole organization that marched forward. That's the key to success.

How does it feel to be behind such achievement?
Mistry: How does it feel to be behind that achievement? Well to me, my principal feeling was immense gratitude to the group. The team, you know hundreds of people who put everything into it, to make it happen.

Chau: We all did our job.

Also, another key to our success is that in an organization like Intel, I feel we are all working together seamlessly from research to pathfinding to development —working very closely under one roof —that is the ingredient to our success.

Mistry: Just to add to what Robert said, what we do really well here at Intel is to have seamless overlap between research and development between development and manufacturing. That is really the key to our ability to bring innovation to the marketplace—the organization overlap and the pathfinding phase that we have wherein the research team and the development team worked together. There is really no difference between a research engineer and a development engineer they are both tasked solving the same problem.

And then at the other end of the spectrum when the time comes to bring the process to manufacturing, we have the manufacturing engineer come and join us in the development fab, and the manufacturing engineer and the production engineer work side by side, doing the same job, so when the manufacturing engineer goes back to their own fab, they can bring up the process and run it the same thing we run it in development.

Ghani: And the thing without having this overlap is the system that we have put in place from early research to manufacturing I don't think big changes like hi-k metal gate can be implemented.

With the intense competition in the industry, it is a given that you have to be on your toes all the time, right?
Mistry: I think we constantly try to be ahead of the industry in terms of CMOS technology. That is certainly our goal, and hope we will be successful as we move forward.

Anything you would like to say to our Asian design engineers readers?
Mistry: I have two things to say. At Intel we believe Moore's Law is alive and well and scaling still provides benefits that we have been accustomed to in terms of resisting the cost of transistor, and improving the power performance of the transistor so we feel Moore's Law has a lot of life still left in it so our industry will continue to evolve because of that.

Second, if you look at the 45nm process that we are bringing to market right now, I think one of the unique advantages that we have as an integrated device manufacturer is that we have all of the capabilities in-house, all the way from making mask to developing the process technology doing the lithography development during the transistor development during the design activity for the microprocessor design and the package development as well. Having all of that inside one company, we feel it is a tremendous advantage going forward as the interaction between patterning, design-for-manufacturability, interactions between design and manufacturing become more and more prevalent, the ability to work well all together across organizational boundaries is the key to our success and for the success of the industry as well.

Ghani:: We have heard many times about the impending demise of Moore's Law. I have heard it when I was a student and very respected professors will be citing all the reasons why they think Moore's Law will not survive, and you know the limitations they have highlighted, we surpassed, and gone past those.

What you see here is high-k metal gate strain and other features, really highlighting the very innovative nature of this field, people who work in this area. I think such innovations, at least for the next 10 years or so, people will come up with more innovation and find ways of extending Moore's Law and show up with better products.

Chau:: I think we have of firepower to continue with Moore's Law. However, those innovations that they talked about really come from research, and at Intel, we have a very strong research program, and through research, we believe we can continue to have innovation for many, many more years to come.

- Celeste dela Torre
EE Times-Asia