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Achieve processor energy savings with AVS

Posted: 03 Dec 2007 ?? ?Print Version ?Bookmark and Share

Keywords:AVS? voltage scaling? processor energy savings?

With the wave of high data rate infrastructure expanding across the globe and the media-intensive devices now available to consumers, feature-rich handsets will be used almost continuously while relying on battery capacity similar to that of a voice-centric device. Imagine all the activities users do on their devices (i.e. download/share/listen to music, download/share photos, browse the Internet, play games, and navigate their way to the movie theaters and restaurants etc.). It is becoming a 24/7 lifestyle that requires extended device runtime.

While user experience is important to end users, network operators and content owners also depend on these new media-intensive features, and their extended use, for their revenue. Limited battery life can mean limited revenue as well.

The concept of voltage scaling and energy savings can be understood by looking at the energy consumption equation of digital systems: E = {(CVDD2f) + (VDDILEAK)}t, where the dynamic terms include C (circuit capacitance), VDD (supply voltage) and f (clock frequency); and the static term is dominated by the ILEAK (leakage current) of the digital gates. It is readily seen why a common energy-saving technique used in digital circuits involves scaling down f and VDD of the processing engine to reduce energy expenditure. Two common voltage scaling techniques are dynamic voltage scaling (DVS) and adaptive voltage scaling (AVS).

DVS is an open-loop approach that adjusts the voltage and frequency in pre-characterized parings or with a voltage vs. frequency look-up table. These voltages need to be high enough to maintain functionality over all parts and temperatures. While this open-loop approach yields a reasonable amount of energy savings, it cannot achieve all the energy savings possible.

AVS is a close-looped approach that reduces the supply voltage to the minimum possible while still allowing tasks to be completed in time. While DVS regulates the supply voltage to a pre-characterized value that is fixed and ignores process, temperature, and power supply variation, AVS takes all these factors into account while determining the optimal supply voltage level and guaranteeing minimum energy consumption.

How AVS works
AVS is a system-level solution that reduces the energy consumption of digital SoC solutions by allowing independent and automatic control of the supply voltage of each of the separate processing engines in the SoC. The technology embeds a synthesizable Advanced Microcontroller Bus Architecture (AMBA)-compliant core, the Advanced Power Controller (APC) into the SoC.

The APC enables the system to implement either dynamic voltage scaling or full adaptive voltage scaling on the target SoC. The APC ensures that the supply voltageand thus the energy consumed in digital logicis minimized for the current SoC clock frequency through close interaction with the power delivery system, minimizing demands on the power source while providing peak efficiency.

The APC interfaces to the rest of the system using three interfaces: AMBA-compliant host interface, Clock Management Unit (CMU) interface and the open standard PowerWise Interface (PWI). The host interface is used to control and configure the APC2 while the CMU interface is used to coordinate voltage and frequency changes.

PWI is a simple and fast (up to 15MHz), two-pin serial interface specifically designed to meet the needs of AVS and DVS while offering extensive programming options for versatile applications. The latest PWI 2.0 standard supports multiple SoCs and peripheral devices on the same bus. The PWI interface is used to communicate power management information to external Energy Management Units or to control other peripheral devices.

- Joy Taylor
Senior Product Marketing Engineer
National Semiconductor Corp

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