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Tool designs massively parallel processors

Posted: 10 Dec 2007 ?? ?Print Version ?Bookmark and Share

Keywords:software development tool? DSP? FPGA massively parallel processors?

Ambric, a fabless semiconductor company that manufactures the Am2045B teraOPS-class processor chip, has released aDesigner, a software development tool suite for the Ambric Am2000 family of scalable, massively parallel processor arrays (MPPAs).

aDesigner uses Ambric's structured object programming model (SOPM) to make software development practical for embedded application developers who need to harness the power of massively parallel processor-based systems.

The aDesigner IDE has a powerful GUI that serves as a cockpit for the user to program the Am2000 MPPA. The design creation, simulation, compilation, realization and debugging tools, which are included in the tool suite, enable easy creation, verification and real time execution of the objects that collectively form the complete design. The aDesigner IDE uses the widely deployed Eclipse framework, a mature, familiar platform to accelerate developers' migration.

Ambric's built-in simulator provides cycle-accurate behavior of the design. The compiler has a unique optimization capability that takes into account user-defined constraints at both the local and global levels. The realization tool enables mapping of the design on single or multiple devices. And the debugger enables bugs to be detected during design simulation and design execution in the real-time hardware system. Together these tools work seamlessly within aDesigner.

The Ambric SOPM is a patented technology that leverages over 20 years of research on programming massively parallel processors on single or multiple devices. The Am2000 family architecture was built around this model, which results in a tight coupling between the programming model and the device architecture.

Conventional tools, looking for parallelism in large blocks of code, use heuristic, best- effort techniques to break the code into multiple threads. Developers targeting high- performance applications find that code executing on multiple threads does not meet their goals. Code frequently stutters, deadlocks and is very hard to debug. In contrast, during system design, SOPM allows developers to describe well-defined relationships between software components, creating solutions that are robust enough to meet the challenges of real time execution. Using SOPM, customers are able to bring up and execute applications in weeks, as compared to months with conventional software tools.

The aDesigner suite enables a deterministic approach to programming because data transfer and execution control are combined into a single mechanism that eliminates global timing closure issues. It also enables a very practical approach by providing the ability to directly map software objects onto processors on the chip. What you see in software is what you get on the Am2000 MPPA. There are no intermediate results to be back-annotated and no language database to be stored- just straightforward SOPM-based software code executing on the Am2000-based hardware.

Programming DSPs and FPGAs is time consuming and error prone. With aDesigner, it is claimed that development time is slashed because hierarchical objects can be created and then reused to easily build complex objects in software and on the Am2000 MPPA. Also, these objects can be encapsulated and replicated on the same MPPA as well as across multiple MPPAs. Executing these objects then becomes a simple task because timing characteristics of the object are self-contained and there is no global timing closure issue to deal with.

The aDesigner software development tool suite is available today to qualified developers. General availability will be January 2008. List price starts at $1,495.

- Clive Maxfield
Programmable Logic DesignLine

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