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PLL-based clock generators create ultralow jitter

Posted: 13 Dec 2007 ?? ?Print Version ?Bookmark and Share

Keywords:clock generators? ultralow jitter? PCIe? Ethernet?

ON Semiconductor Inc. has launched PLL-based devices for creating ultralow-jitter quality clocks that improve timing accuracy, increase design flexibility and lower cost for PCIe, Ethernet and FB DIMM applications. The NB3N3002 and NB3N5573 3.3V clock generators are an expansion of the company's PureEdge clock generation product portfolio. They can create selectable host clock signal levels (HCSL) and sub-picosecond jitter quality clocks at 25-, 100-, 125- and 200MHz. Silicon-based clock generation ICs, such as the NB3N3002 and NB3N5573, are said to be inherently simpler to manufacture than more expensive crystal oscillators, which results in both lower overall system costs and shorter lead times.

The NB3N3002 generates one differential HCSL output clock, while the NB3N5573 delivers dual output. Employing advanced 0.25?m CMOS technology, the devices significantly outperform competitive devices with phase noise comparable to surface acoustic wave crystal oscillators, said ON Semiconductor. These devices generate high-quality clocks from a low cost 25MHz crystal with four selectable output frequencies and integrated 1:2 fanout buffer (NB3N5573). The device provides phase noise of -130dB relative to the carrier per hertz (dBc/Hz) at 100KHz offset from the carrier frequency.

The NB3N5573 is a pin compatible drop-in replacement for the competitive function device ICS557-3. The NB3N5573 provides better jitter performance and was implemented without the Spread Spectrum feature making it a better value where SSM is not required, said ON Semiconductor.

The devices are offered in a 5.0mm x 4.4mm Pb-free TSSOP-16 packages, and priced at $1.80 each in quantities of 2,500.

- Gina Roos

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