Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

IMEC's 'Apollo' moves closer to goal

Posted: 17 Dec 2007 ?? ?Print Version ?Bookmark and Share

Keywords:Apollo? sub-45nm? design tools?

Apollo, a three-year strategic research program being pursued by Belgium's Interuniversity Microelectonics Center (IMEC), is producing results in its quest to provide the technology for efficient migration to 4G communications and multiprocessing in the sub-45nm era. It is also set to help drive business at IMEC's latest spin-off.

A follow-on from IMEC's multimode multimedia (M4) project, Apollo began in April and is expected to run through mid-2010, although a few IC tape-outs at 90nm are still pending as conclusions to the M4 work. Like M4, Apollo aims to produce a multistandard mobile terminal as an industry pathfinder; but while M4 targeted a software-defined radio, Apollo is expected to move on to a cognitive-radio terminal capable of operating at carrier frequencies up to 60GHz.

The project is targeting 45nm IC implementations but is already producing results in terms of architectural considerations for power-efficient multiprocessing and design tools, researchers said. In six months, the project has produced a multiprocessing support tool and an approach to variability-aware design.

Apollo is organized as eight standalone but interlinked technology programs including technology-aware design (TAD), processor and compiler architecture, and multiprocessor support, according to Serge Vernalde, technical business director for nomadic embedded systems at IMEC.

The Adres processor, with its VLIW processing and reconfigurable array, is at the heart of the M4 baseband chip and is likely to be recast under Apollo for multiprocessor deployment.

Similarly, the Scaldio CMOS analog front-end developed for M4, operating at up to 6GHz, will not only get a redesign at that frequency but will be complemented by a 60GHz CMOS AFE. This is expected to tape out in 45nm digital CMOS in Q2 2008, said Liesbet Van der Perre, IMEC's scientific director for wireless systems.

M4S road map
The move to Apollo within IMEC adds value to M4S NV, according to Rudi Lauwereins, IMEC VP of design research. M4S was created to commercialize aspects of M4. "Apollo provides a road map for M4S," said Lauwereins.

Samsung, a key partner in the M4 project, is expected to have renewed its subscription. Meanwhile, Qualcomm has signed on the TAD program within Apollo. TAD's goal is to raise manufacturing reliability and yield issues up to the system-design level. Miguel Miranda, a senior scientist at IMEC, explained how relaxing timing constraints can typically improve yield, albeit with a minor penalty for average energy consumption.

Even though ultralow energy consumption is a goal of the Apollo project, being able to consider yield trade-offs is likely to be a valued addition to design optimization, particularly as guardbanding for process variation is likely to negate the benefits of process shrinks.

The Adres processor remains the basic processor for Apollo, but extensions are aimed at upcoming industrial processor architectures, according to Diederik Verkest, science director for design technology at IMEC. "Adres was already power-efficient; with Adres we can reach 16 to 20 instructions per cycle [IPC]. Now we want to see how to embed multiple threads to better fill the array," said Verkest. The target is an IPC count of 50.

Ready for lift-off: IMEC's Apollo is organized as eight standalone but interlinked technology programs.

The researchers aim to split Adres up and separate the controlling VLIW processor from the 4 x 4 array. "We are also investigating commercial solutions," Verkest said. "TI's C64 is a VLIW machine, and there are lots of new architectures, such as Silicon Hive."

The reconfigurable array is likely to go to 8 x 8 to provide greater scope for parallelism before putting down multiple processors on silicon.

Other strategies
Extracting parallelism from application software is key to improving performance and power efficiency. To that end, IMEC has developed the Multiprocessing Parallelization Assistant (MPA). Based on parallelization directives provided by the designer, the MPA can check a parallelization scheme, insert necessary communication and synchronization primitives, and generate code for the multiple processors. Verkest said the tool allows rapid exploration of parallel mappings starting from sequential C code.

In addition, IMEC has developed and is supporting CleanC, a coding style with 28 guidelines and restrictions on how to write C code that is multiprocessor friendly, Verkest said. To help software developers adhere to this style, IMEC developed an analysis tool that can analyze software and flag violations of the CleanC programming style. User-guide code transformations can then be applied to make the code compliant. The suite has been integrated into the Eclipse 3.3 development environment, specifically within CDT4.0, a version of the C/C++ developer tooling, Verkest said.

- Peter Clarke
EE Times

Article Comments - IMEC's 'Apollo' moves closer to goal
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top