Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > FPGAs/PLDs
?
?
FPGAs/PLDs??

Analyze simultaneous switching noise in PCBs

Posted: 17 Dec 2007 ?? ?Print Version ?Bookmark and Share

Keywords:simultaneous switching noise? FPGA output buffer? PCBs?

CMOS technology enables a single FPGA device to have many I/O interfaces. Recently, low power has emerged as a principal theme in high-speed I/O interfaces, and voltage reduction offers the most effective means of minimizing power consumption. As a result, the noise margin of these I/O interfaces has become smaller. Thus, it is essential for FPGA users to quantify system-level simultaneous switching noise (SSN) in a chip/package/PCB environment.

This article from Altera offers a systematic SSN overview with the focus on SSN caused by FPGA output buffers. This noise is widely known as simultaneous switching output noise (SSO), and is differentiated from the SSN caused by input buffers. A description of the causes of system-level SSO is presented, and a hierarchical system-level SSO modeling methodology is proposed. A procedure for correlating the SSO models to frequency- and time-domain measurements is provided and several PCB design methodologies for minimizing SSO in PCBs are offered.

View the PDF document for more information.




Article Comments - Analyze simultaneous switching noise...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top