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FPGAs exceed 1,067Mbit/s DDR3 interface speed

Posted: 18 Dec 2007 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA? DDR3 memory interface? JESD79-3 JEDEC DDR3 SDRAM standard?

Altera Corp. has announced it has achieved DDR3 memory interface speeds in excess of 1,067Mbit/s with its Stratix III FPGAs. This is provides a 33-percent advantage in memory performance over competing FPGA solutions, the company claimed.

The higher memory bandwidth enables new communications, computing and video processing applications that were either previously impossible or required doubling the number of memory banks. The FPGAs demonstrate full compliance to the JESD79-3 Jedec DDR3 SDRAM standard, including the performance-critical read/write-leveling specification for maximum system performance.

"The performance, cost, density, and power benefits that DDR3 memory provides, in conjunction with the highest performance and lowest power of Stratix III FPGAs, is essential to a wide range of communications, signal processing, high-performance computing and image processing applications," said David Greenfield, senior director of product marketing, high-end products at Altera. "Stratix III FPGAs are the only FPGAs designed for fully compliant DDR3 SDRAM DIMM support and the only FPGAs to exceed 533MHz operation."

In addition to higher memory interface speeds, Stratix III FPGAs demonstrate 29-percent lower power consumption and a 25-percent performance advantage, as compared to competing solutions, making the device family ideal for high-performance applications that require the lowest possible power.

Designed to address the benefits of DDR3 memory, Altera's Stratix III family is the only FPGA in the industry to include read and write leveling, I/O delay for DQ de-skew, dynamic on-chip termination, and the use of a reconfigurable PLL to compensate for voltage and temperature variations. In addition, Altera's Quartus II software ver 7.2 includes a DDR3 PHY wizard and controller intellectual property, which substantially simplifies high-performance memory interface design by automatically adapting to DIMMs from a variety of memory suppliers.

Altera Stratix III FPGAs featuring DDR3 memory bandwidth capabilities of 533MHz are already available.

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