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How to build efficient power supplies

Posted: 18 Dec 2007 ?? ?Print Version ?Bookmark and Share

Keywords:PoE? efficient power supply? MOSFET?

By Frank Cathell
Senior Applications Engineer, ON Semiconductor Corp.

As a result of the IEEE Standard 802.3AF, it is now possible to inject DC power through Ethernet data transmission lines to power Ethernet communication devices as long as the end power requirement is less than 13W. The parametric details of DC power transmission and the associated terminology is outlined in this IEEE document. PoE consists of two power entities: Power Sourcing Equipment (PSE) and Powered Devices (PDs). The PSEs typically provide 48Vdc nominal to the LAN cables while the PDs are small DC/DC converters at the load end of the cables that transform the 48V to logic levels such as 5.0Vdc or 3.3Vdc or both, to power the communications equipment. The PDs should be able to operate with a maximum average input power of 12.95W and tolerate an input voltage range of 36-57Vdc. In addition, a certain "protocol" is required in which the PD is detected (Signature Mode) and then classified (Classification Mode) according to its maximum power level.

In addition to the signature and classification circuitry, the PD must also include circuitry to limit the inrush current from the PSE to 400mA when the input voltage is applied, and to prevent any quiescent currents or impedances caused by the DC/DC converter to be ignored during the signature and classification processes.

Shown is a PoE powered device schematic (Click to view full image)

Circuit details
Referring to the schematic in Figure 1, the input signature and classification circuitry is designed around a few discrete ON Semiconductor parts that include the TL431 programmable reference, a 2N7002 signal level MOSFET, a 2N5550 npn transistor, an NTD12N10 MOSFET and several Zener diodes and a few resistors and capacitors. For signature detection, a 24.9K resistor (R1) is placed directly across the input. Note that during signature detection, the input voltage is below 10V and the constant current source formed by U1, Q2 and R4 is off because of the 9.1V Zener that must be overcome to bias this circuit. Note also that MOSFET Q3, which functions as a series input switch in the return leg of the DC/DC converter, will be off until the input voltage exceeds approximately 27V. This voltage is the sum of D2's Zener voltage and the gate threshold of Q3.

As the voltage is ramped up to the classification level, D1 conducts above approximately 9.8V and the current source formed by U1, Q2 and resistor R4 turns on and the current is precisely limited by the reference voltage of U1 (2.5V) and the classification resistor R4.

Once classification is verified the input can now ramp up to the nominal 48V. Once this voltage exceeds the sum of Q3's gate threshold and D2's Zener voltage, Q3 will start to turn on. It will not turn on abruptly, however, but will operate in its linear region shortly due to the RC time constant created by R6 and C2. The momentary operation in the linear region allows for inrush current limiting because Q3 will act like a resistor during this period. D3 clamps the voltage on Q3's gate to 15V, while R5 provides a discharge path for C2 when the input from the PSE is off. MOSFET Q1 will also turn on at the same voltage level as Q3, and this will switch off the U1/Q2 current source to reduce additional current drain from the input.

Converter operation
The DC/DC converter is designed around ON Semiconductor's monolithic NCP1031 switching regulator IC (U2). For a 5W maximum output, the converter is configured as a discontinuous mode (DCM) flyback topology with the conventional TL431 and optocoupler voltage feedback scheme. Modifications to the transformer design and the control loop compensation network for continuous conduction mode flyback operation will allow up to 6.5W (1.3A) output. The input utilizes a differential mode pi filter comprised of C3, L1 and C4.

Control chip startup is accomplished when the undervoltage terminal at pin 6 exceeds 2.5V. The resistor divider network of R7, R8, and R9 sets the chip's under and overvoltage levels to 35V and 80V, respectively. Internal startup bias is provided thru pin 8, which drives a constant current source that charges Vcc capacitor C7. Once U2 has started, the auxiliary winding on transformer T1 (pins 2, 3) provides the operating bias via diode D4 and resistor R11.

The network of C5, D6 and R10 clamps voltage spikes caused by the leakage inductance of T1. The actual power rating on R10 will be a function of the primary-to-secondary leakage inductance of T1, and the lower the better. Capacitor C6 sets the switching frequency of the converter to approximately 220kHz.

Because of the required secondary isolation, a TL431 (U4) is implemented as an error amplifier along with optocoupler U3 to create the voltage sensing and feedback circuitry. The internal error amplifier in U2 has been disabled by grounding pin 3, the voltage sense pin, and the amplifier's output compensation node on pin 4 is utilized to control the pulse width via the optocoupler's photo transistor. The output voltage sense is divided down to the 2.5V reference level of the TL431 by R16 and R17, and closed loop bandwidth and phase margins are set by C9 and R15 for DCM operation. Additional components (C14, C15 and R12) are required for feedback loop stabilization if configured for CCM flyback operation. C8 on the primary side provides noise decoupling and additional high frequency roll off for U2. This implementation provides output regulation better than 0.5 percent for both line and load changes, and a closed loop phase margin of better than 50.

Output rectifier D5 is a three-amp Schottky device for enhanced efficiency, and the pi network comprised of C11, L2 and C12 filters the output voltage. Typical peak-to-peak noise and ripple on the output are below 100mV under all normal load and line conditions. C13 provides for additional high-frequency noise attenuation. Typical input to output efficiency is in the area of 75 percent at full load (Figure 2). Higher efficiencies can be achieved by replacing D5 with a MOSFET-based synchronous rectifier circuit.

Figure 2: Typical input to output efficiency is in the area of 75 percent at full load.

The internal peak current limit circuit in the NCP1031 provides overcurrent protection. The circuit can provide a continuous output current of 1.3A at 25C with surge up to 1.5A when configured as a CCM flyback before over-current and/or over-temperature limiting ensues. When configured for the discontinuous mode, the current is limited to about 1.0A with a 1.2A peak.

Magnetics design
The discontinuous mode flyback transformer design is detailed in Figure 3 and the continuous mode transformer is shown in Figure 4. In the design of flyback transformers, it is essential to keep the windings in single layers and evenly spread over the window length of the core structure to keep leakage inductance minimized. In this application, this was easily achieved with a small EF16 ferrite core from Ferroxcube.

Figure 3: Shown is the discontinuous mode flyback transformer design.

Figure 4: Shown is the continuous mode transformer design.

In discontinuous mode flyback operation, the inductor current falls to zero before the MOSFET switch is turned on again. This mode of operation causes the output to have a first order filter network characteristic and, as a consequence, feedback loop stabilization is simple and wide bandwidth for good output transient response can be achieved. This operational mode unfortunately, results in higher peak switch currents and limits the power output of this circuit due to the internal current limit set point and the thermal protection circuits in the NCP1031. With continuous current mode operation, where the MOSFET can turn back on before the inductor current is zero, the peak switch current is less, and so higher power outputs can be achieved without over-current protection intervention. There is a cost, however, to this latter mode of operation in that the control loop bandwidth must be made lower with a resulting poorer transient response to load and line variation. CCM operation introduces a right half-plane zero to the power topology response characteristic which may need to be compensated for with the additional feedback components shown in Figure 2, if proper feedback stability is to be achieved. CCM may also generate more EMI due to the fact that the output rectifier must now be force commutated off.

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