Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Hybrid ASIC cuts SoC development costs

Posted: 26 Dec 2007 ?? ?Print Version ?Bookmark and Share

Keywords:hybrid ASIC? standard cell? EDA tool? SoC development?

Mixed-signal ASIC company ChipX Inc. has introduced a hybrid ASIC, the implementation of a structured ASIC as IP on a standard cell device.

The development approach allows for rapid and economical product line development, saving companies an average of three-to-five hundred thousand dollars in NRE and tooling costs and enabling them to introduce derivative products two-to-three months faster than today's methodologies allow.

A SoC developed in standard cell technology results in the smallest device size and best performance, but it incurs significant up-front costs and long manufacturing lead times. Producing a series of custom products becomes capital intensive and often prohibitive for many companies. Structured ASICs solve the problem of high up-front costs and long lead times but the level of integration is often limited to available platforms and sizes.

Hybrid ASIC combines standard cell logic and I/Os, compiled memory and mixed-signal IP with a predefined configurable logic in a structured ASIC core and configurable memory. The designer decides what functionality is built in the configurable portion of the chip and ChipX customizes a structured ASIC IP core in any shape or size (desired for the section of the design likely to be altered in the future.

70% savings
Configurable memory blocks and configurable I/Os can also be inserted, offering various levels of flexibility and upgradeability. In the case of a derivative product, only the changing portion of the design needs to be processed. Consequently, development time can be reduced to a fraction of the initial development time- typically tens or hundreds of thousand gates are processed instead of millions of gates. The fabrication time can be reduced to a few layers of metal compared with 30 to 40 layers and the NRE cost is slashed by 70 percent or more.

Hybrid ASIC products are customer specific and can have up to 10M ASIC gates and 10Mbit of memory. ChipX offers a wide range of IP, including PCI Express, USB 2.0 OTG, Video DAC and ADC, synthesizable processors from ARM, Beyond Semiconductor, DDR/DDR2 PHYs and controllers, as well as over 200 blocks of synthesizable IP. In addition, hybrid ASIC designs follow industry standard design flows and require only standard EDA tools.

Typical applications for Hybrid ASIC include video compression or data encryption for designers who wish to implement the same device with different compression or encryption schemes. The implementation of an ASIC with a pre-standard interface or algorithm is also ideal for Hybrid ASIC. In these cases, the potentially variable design logic is placed in the configurable structured ASIC area. A proliferation of new products can quickly and easily be built by changing just the design in this area, without requiring additional work on the fixed portions of the design

"Designers of consumer multimedia products prefer to develop complete product families that give buyers a variety of choices. For example, one member of a video product line might have an H.264 CODEC only while another might add DivX," said Michelle Abraham, principal analyst, Multimedia. "Consumer electronic manufacturers could greatly benefit from a fast, inexpensive ASIC methodology that enabled them to implement multiple products, and rapidly enter and dominate new market segments.

"Hybrid ASICs allow our customers to build several generations of customized products or various derivatives quickly and effectively," said Elie Massabki, VP of marketing at ChipX. "For the first time, we can offer a solution that slashes the cost of chip development without introducing compromises."

ChipX's Hybrid ASIC gives developers the benefits of standard cell and structured ASICs without the tradeoffs. Turnaround time for logic changes can be as short as 6 weeks, from tape-out to packaged and tested prototypes with NREs starting as low as $99,000 in 0.13?. ChipX hybrid ASIC is available in 0.13? CMOS process and designs can start immediately.




Article Comments - Hybrid ASIC cuts SoC development cos...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top